Semiconductor Chip Processing Apparatus Hardware Area Reduction

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Solution Overview

Problem

Semiconductor chips with multiple processor elements (PEs) face inefficiencies due to large hardware occupation and power dissipation, especially when implementing fixed functions, which can lead to reduced chip yields and increased area usage, as existing technologies result in PEs being at least 10 times more hardware-intensive than standard cells.

Innovation Solution

The semiconductor chip design incorporates at least two PEs with the same interface specifications but differing internal structures, allowing for functional replacement, including a redundant PE for backup purposes, and the use of wired-logic circuits to simplify or remove unused functions, thereby reducing hardware volume and power dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If PE array is used to implement fixed functions, then functional capability is achieved, but hardware area increases at least 10 times compared to standard cells

Engineering Contradiction:

Improvefunctional capabilityVSAvoidhardware area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by differentiating between processing elements that implement fixed functions and those that maintain full PE capabilities. Fixed-function PEs are optimized for specific operations (like DCT circuits) with simplified internal structures, while other PEs retain complete functionality. This localized optimization reduces overall hardware area while preserving necessary functional capabilities.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the operational parameters of certain PEs by fixing their functions through configuration data. Once a PE is designated for a fixed function, its internal structure and operational parameters are locked to that function, transforming it from a reconfigurable unit to a dedicated functional unit with reduced hardware requirements.

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If PE array is used to implement fixed functions, then functional capability is achieved, but power dissipation increases correspondingly

Engineering Contradiction:

Improvefunctional capabilityVSAvoidpower dissipation

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The patent reduces power dissipation by applying local quality optimization to fixed-function PEs. These PEs have simplified internal structures tailored to specific operations, eliminating the power consumption associated with unused functional units and reconfigurable logic that would be present in full PEs.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent extracts and removes unnecessary functional components from PEs that are designated for fixed functions. By taking out unused logic units, multiplexers, and reconfigurable elements, the hardware area and power dissipation are reduced while maintaining the required functional capability.

Inventive Principle:

Principle #2Taking out (Extraction)

3Adaptability or versatility

If discrete cosine transformation circuits are used as fixed functions, then image compression and expansion functions are achieved, but hardware space increases at least 10 times compared to standard cells

Engineering Contradiction:

Improveimage processing functionVSAvoidhardware space

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by designating specific PEs for DCT circuit functionality while maintaining other PEs as fully reconfigurable. The DCT-specialized PEs have optimized internal structures for image compression and expansion operations, reducing hardware space compared to using full PEs for all functions.

Inventive Principle:

Principle #3Local quality

4Productivity

If processing apparatuses are reduced for fixed functions, then hardware efficiency improves, but redundancy for backup purposes is reduced

Engineering Contradiction:

Improvehardware efficiencyVSAvoidchip yield

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements beforehand cushioning by incorporating redundant PEs that can serve as backups for failed processing elements. Even though fixed-function PEs use reduced hardware, the system maintains redundancy by having additional PEs available to take over in case of failures, thus cushioning against yield losses from manufacturing defects.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent applies universality by designing PEs with configurable functions that can be assigned different roles through configuration data. Redundant PEs can be programmed to match the functionality of failed PEs, providing backup capability without requiring identical hardware structures for all functions.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS7900180B2Semiconductor chip using specification interface

Publication Date: 2011.03.01 SONY GROUP CORP

AI summary

Disclosed herein is a semiconductor chip including at least two processing apparatuses which comply with the same interface specifications and which differ in internal structure, wherein at least one of the processing apparatuses is constituted functionally to replace at least one processing apparatus.