Semiconductor Chip Stacking via Insulating Layer Vias
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Solution Overview
Problem
Current chip-on-wafer (COW) technologies face challenges such as low productivity and high production costs due to the need for forming deep via holes and metal filling, which increases time and material usage, and results in non-uniform via hole diameters leading to unreliable connections.
Innovation Solution
A semiconductor device production method where separate semiconductor chips are stacked on a substrate with an insulating layer, allowing for signal transmission between layers without the need for deep via holes, using a resin layer to seal and connect the chips, reducing production costs and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep via holes are formed through semiconductor chips and metal filling is performed to connect chips, then connection reliability is improved, but productivity decreases and production costs increase
Solution Approach 1:
The invention segments the connection process by forming via holes only in the insulating layer rather than through the entire chip thickness. This segmentation allows the connection structure to be divided into manageable parts: via holes in the insulating layer, bump electrodes on chip surfaces, and metal connections, eliminating the need for deep through-chip via holes and improving productivity while maintaining reliability
Solution Approach 2:
The invention transitions from a vertical through-chip connection approach to a multi-dimensional connection scheme where bump electrodes extend from chip surfaces into via holes in the insulating layer. This dimensional change allows connections to be established without forming deep via holes through the chip substrate, thereby improving productivity while maintaining connection reliability
2Reliability
If deep via holes are formed and filled with metal to connect semiconductor chips, then signal transmission between chips is enabled, but production costs increase due to time and material consumption
Solution Approach 1:
The invention extracts the via hole formation process from the chip substrate and relocates it to the insulating layer only. This extraction eliminates the need to form deep via holes through the expensive semiconductor chip material, reducing both time consumption and material usage while maintaining the essential function of enabling signal transmission between chips
Solution Approach 2:
The invention uses the insulating layer as a disposable medium for forming via holes, rather than forming via holes through the valuable chip substrate. The insulating layer serves its purpose of providing a medium for via hole formation and metal filling, then allows bump electrodes to establish connections, effectively reducing production costs by avoiding damage to expensive chip materials
3Adaptability or versatility
If via holes are formed by dry etching with varying sizes, densities, and depths, then connection flexibility is achieved, but via hole diameter uniformity deteriorates leading to reduced reliability
Solution Approach 1:
The invention applies local quality by forming via holes with uniform dimensions in the insulating layer, where the insulating layer provides a consistent medium for via hole formation. This local uniformity in the insulating layer ensures consistent via hole diameters and reliable connections, while still allowing flexibility in connecting different chip configurations through appropriate via hole positioning
Data Source
AI summary
A semiconductor device production method where separate semiconductor chips are stacked on a semiconductor substrate having a main surface on which multiple semiconductor chips including semiconductor integrated circuits are formed, the semiconductor chips in different layers are connected to each other to enable signal transmission, and a structure formed thereby is separated into multiple stacks of the semiconductor chips. The method includes a first step of forming an insulating layer on the main surface of the semiconductor substrate; a second step of stacking the separate semiconductor chips, which include the integrated semiconductor circuits on main surfaces thereof, via the insulating layer on the semiconductor chips formed on the semiconductor substrate such that opposite surfaces of the separate semiconductor chips opposite to the main surfaces face the insulating layer; and a third step of forming connecting parts that enable signal transmission between the semiconductor chips in different layers.