Semiconductor Chip Thinning via Segmented Grinding and Polishing

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Wafer level packaging in the semiconductor industry faces challenges due to mechanical stress-induced cracks and damage from grinding steps, which can lead to further issues during processing, handling, and usage of semiconductor devices.

Innovation Solution

A method involving multiple grinding steps to thin semiconductor chips while minimizing damage, followed by polishing to remove cracked layers and create a planar surface, allowing for the formation of a redistribution layer and fan-out type packages with increased contact area and reduced stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If grinding steps are used to reduce the thickness of the semiconductor die, then the thickness is reduced and packaging performance is improved, but cracks, ridges and valleys are created in the semiconductor material

Engineering Contradiction:

Improvethickness of semiconductor dieVSAvoidcracks, ridges and valleys in semiconductor material

Core Design Contradiction:

Length of moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent divides the single grinding operation into multiple sequential grinding steps with intermediate polishing steps. The first grinding step reduces thickness to a first level, followed by a polishing step to remove damages, then a second grinding step to achieve final thickness. This segmentation allows each step to address specific requirements without compounding damages.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies a polishing step as a preliminary action between the first and second grinding steps. This intermediate polishing removes the cracks, ridges and valleys created by the first grinding before the second grinding occurs, preventing the accumulation and propagation of damages through the semiconductor bulk material.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If additional mechanical stress is applied during processing or handling, then device functionality is maintained, but cracks through the semiconductor bulk material are induced

Engineering Contradiction:

Improvedevice functionalityVSAvoidresistance to stress-induced cracks

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

The patent applies a stress relief layer to the back surface of the semiconductor die before subsequent processing steps. This layer acts as a cushion that absorbs and distributes mechanical stresses during handling, processing, and shipping, preventing stress concentration that would otherwise induce cracks through the semiconductor bulk material.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent converts the potentially harmful grinding damages (cracks, ridges, valleys) into a beneficial structure by applying a stress relief layer that specifically targets and compensates for these damages. The layer transforms the weakened areas into reinforced zones that actually improve the overall mechanical integrity and stress resistance of the semiconductor device.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Ease of manufacture

If standard wafer level package technologies are used, then manufacturing simplicity is maintained, but the number of contact pads is limited

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidnumber of contact pads

Core Design Contradiction:

Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent transitions from a traditional fan-in packaging approach (where contact pads are confined to the top surface area) to a fan-out approach where the stress relief layer on the back surface provides additional area for contact pad formation. This dimensional expansion from 2D top surface to 3D inclusion of back surface allows significantly more contact pads without increasing the chip footprint.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9646856B2Method of manufacturing a semiconductor device including removing a relief layer from back surface of semiconductor chip

Publication Date: 2017.05.09 INTEL CORP

AI summary

A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.