Semiconductor Chip Wiring Layout Preventing Wire Intersections
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Solution Overview
Problem
In semiconductor devices, wires connecting the semiconductor chip and electronic components often intersect with other wires, leading to potential contact and interference issues, which complicates the arrangement and increases the size of the semiconductor chip.
Innovation Solution
The semiconductor device is designed with a semiconductor chip having terminals along one edge, with internal wiring that runs through a region between these terminals, and electronic components positioned between the chip and lead terminals, ensuring that wires connecting the chip and components do not intersect by arranging the terminals and wiring in a manner that diverts along the edge of the chip, preventing contact and simplifying the wiring layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wires are arranged to connect semiconductor chip terminals and lead terminals, then electrical connectivity is achieved, but wire intersections occur causing potential contact and interference issues
Solution Approach 1:
The patent applies dimensionality change by routing internal wiring through the thickness direction (depth dimension) of the semiconductor chip rather than only on the surface plane. Specifically, wiring layers are stacked in multiple levels (first internal wiring layer, second internal wiring layer, etc.) along the thickness direction, allowing wires to connect terminals without intersecting on the same plane. This vertical stacking approach transforms a 2D wiring problem into a 3D solution, eliminating wire intersections while maintaining electrical connectivity.
2Device complexity
If terminals are arranged along one edge of the semiconductor chip, then wiring simplification is achieved, but placement flexibility for circuit components is reduced
Solution Approach 1:
The patent segments the wiring function by separating external terminals (on the front surface) from internal wiring layers (in the thickness direction). Terminals are grouped along one edge on the front surface for simplified external connection, while the internal wiring is divided into multiple stacked layers that can independently route signals. This segmentation allows the terminal arrangement to be optimized for wiring simplicity while the internal wiring layers provide the flexibility needed for various circuit placements.
Solution Approach 2:
By moving wiring routing into the thickness direction with multiple stacked wiring layers, the patent gains additional spatial freedom. This vertical dimension allows circuit components to be placed more flexibly on the front surface without worrying about wire intersections, as the wiring occurs in different vertical levels. The terminal grouping along one edge simplifies external connections while the internal wiring layers accommodate diverse circuit placement requirements.
Data Source
AI summary
A semiconductor device includes a semiconductor chip including a circuit having a predetermined function, at least one first terminal connected to the circuit, and plural second terminals not connected to the circuit, the first and second terminals being formed along one edge of the semiconductor chip; plural third terminals provided at positions outside of the semiconductor chip and opposing the one edge, each of the plural third terminals being connected to one of the plural second terminals by a respective first wire; and an electronic component provided between the semiconductor chip and the third terminals, the electronic component including a fourth terminal that is connected to the first terminal by a second wire and is disposed below some of the first wires, wherein the first terminal is disposed at a position such that the first and second wires do not intersect.