Semiconductor Circuit dV/dt Malfunction Prevention
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Solution Overview
Problem
Conventional semiconductor circuits face malfunctions due to self-excited and separately excited dV/dt abrupt changes in floating potentials, particularly during light load driving and delayed response, which necessitate increasing the width of one-shot signals, leading to prolonged high voltage transistor ON states and increased power consumption, with limited design freedom due to external factor dependencies.
Innovation Solution
A semiconductor circuit design incorporating capacitors for charging and discharging electric charges, signal generating circuits for trigger signal generation, and discharging circuits to manage ON and OFF driven electric charges, allowing for timely discharge and preventing malfunctions without external factor influence, even when dV/dt is applied beyond the one-shot signal input period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of the one-shot signal is increased to cover the time period from turn-on of the P-side semiconductor switching device to the application of dV/dt, then malfunction prevention is improved, but the time period while the high voltage transistor is in ON state becomes longer and power consumption is increased
Solution Approach 1:
The circuit performs preliminary action by generating trigger signals in advance based on the one-shot signal timing. The first trigger signal is generated at the leading edge of the one-shot signal to preemptively discharge OFF-driven electric charges, and the second trigger signal is generated at the trailing edge to discharge ON-driven electric charges, ensuring malfunction prevention without extending the one-shot signal width.
Solution Approach 2:
The patent introduces intermediary elements (first and second capacitors for charge storage, first and second trigger signals, and discharge circuits) that mediate between the one-shot signal and the final switching action. These intermediaries enable precise timing control of charge discharge operations without requiring extension of the original one-shot signal duration.
2Reliability
If the width of the one-shot signal is increased to ensure coverage of dV/dt application time, then malfunction prevention is improved, but design freedom is reduced due to dependency on external factors such as P-side semiconductor switching device type and load average
Solution Approach 1:
The circuit employs feedback mechanisms where the leading edge and trailing edge of the one-shot signal are detected to generate corresponding trigger signals. This feedback-based timing generation ensures that the discharge operations are synchronized with the actual switching events, making the circuit adaptive to different external conditions without requiring manual adjustment of signal width.
Solution Approach 2:
The patent implements dynamic timing control where trigger signals are generated based on the actual timing edges of the one-shot signal rather than fixed time intervals. This dynamic approach allows the circuit to automatically adapt to varying external factors such as different P-side semiconductor switching device types and load conditions, maintaining design freedom while ensuring reliable malfunction prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor circuit effectively prevents malfunctions by ensuring timely discharge of electric charges and maintaining stable operation, independent of external factors, thereby reducing power consumption and enhancing design flexibility.
Implementation Method 1
a first capacitor for charging ON driven electric charges in response to the ON driving signal
Implementation Method 2
a second capacitor for charging OFF driven electric charges in response to the OFF driving signal
Data Source
AI summary
A semiconductor circuit of the present invention comprises a capacitor for charging ON driven electric charges in response to an ON driving signal, a capacitor for charging OFF driven electric charges in response to an OFF driving signal, a signal generating circuit for generating a first trigger signal in response to the ON driving signal, a signal generating circuit for generating a second trigger signal in response to the OFF driving signal, a discharging circuit for discharging the ON driven electric charges in response to the second trigger signal, and a discharging circuit for discharging the OFF driven electric charges in response to the first trigger signal. With this configuration, it is possible to provide a semiconductor circuit and a semiconductor device both of which have a general-purpose malfunction prevention function by which a malfunction due to dV/dt can be prevented without being affected by any external factor.