Semiconductor Circuit Layout for Interference Suppression
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Solution Overview
Problem
Existing semiconductor circuit devices face interference issues between connection wires and digital circuit blocks, leading to potential malfunctions and complexity in memory circuit arrangement, especially when the chip size is limited.
Innovation Solution
The semiconductor circuit device is designed with a configuration where the connection wire does not overlap the digital circuit block in a plan view, with connection pads strategically placed between circuit blocks to shorten wire lengths and reduce interference, allowing for flexible circuit arrangement even on smaller substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection wires are routed to connect analog circuit blocks, then electrical connectivity is achieved, but interference with digital circuit blocks occurs causing potential malfunctions
Solution Approach 1:
The patent applies dimensional separation by arranging the connection wire and digital circuit block in different spatial layers (planar separation). The connection wire is positioned in a first region while the digital circuit block is positioned in a second region, ensuring they do not overlap when viewed from the top surface direction. This spatial separation in the planar dimension effectively prevents interference while maintaining electrical connectivity functionality.
2Area of moving object
If chip size is reduced for miniaturization, then device compactness is improved, but available area for memory circuits and wiring becomes insufficient
Solution Approach 1:
The patent utilizes planar dimensional optimization by strategically positioning connection wires and circuit blocks to maximize space utilization. By ensuring connection wires do not overlap with digital circuit blocks in plan view, the layout achieves efficient space usage that accommodates memory circuits and wiring on smaller substrates, enabling device miniaturization while maintaining manufacturing feasibility.
Solution Approach 2:
The patent divides the substrate into distinct regions: a first region for connection wires and a second region for digital circuit blocks. This segmentation approach organizes circuit elements into separate functional zones, preventing interference while optimizing the overall chip layout for compactness and manufacturability.
3Quantity of substance
If memory circuits are arranged in multiple areas to fit chip constraints, then storage capacity is achieved, but connection and addressing become complicated
Solution Approach 1:
The patent segments the substrate into distinct functional regions, with connection wires positioned in a first region and digital circuit blocks (including memory circuits) positioned in a second region. This spatial segmentation simplifies the connection and addressing of memory circuits by providing clear regional separation, reducing wiring complexity even when accommodating substantial storage capacity.
Data Source
AI summary
A semiconductor circuit device includes: a semiconductor substrate; and a first circuit block including an analog circuit as a component, a second circuit block including a digital circuit as a component, a connection pad, and a connection wire electrically connecting the connection pad with the first circuit block, all of which are arranged on the semiconductor substrate. The connection wire is provided so as not to overlap the second circuit block in a plan view.