Semiconductor Device Ringing Noise Suppression via Integrated CR Snubber
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Solution Overview
Problem
Conventional semiconductor devices experience ringing noise due to parasitic capacitance and inductance when switching elements are turned ON and OFF, leading to overcurrent and overvoltage issues that can damage the semiconductor chips.
Innovation Solution
Incorporating a capacitor and resistor in series in the conduction path between the P and N terminals, with the capacitor having an electrostatic capacitance of 1.0 to 8.0 nF and the resistor having a resistance value of 2.0 to 7.0 Ω, functioning as a CR snubber circuit to suppress ringing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor and resistor are added to suppress ringing noise, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines the capacitor and resistor into a single integrated component unit that is mounted within the semiconductor device housing. This merging approach allows the noise suppression function to be added without proportionally increasing device complexity, as the two components work together as a coordinated system rather than separate elements.
Solution Approach 2:
The capacitor and resistor serve as intermediary elements between the switching element and the external circuit. By placing these components in the signal path, they mediate the electrical transitions and suppress ringing noise without requiring fundamental changes to the switching element itself, thus improving reliability while maintaining relatively simple device architecture.
2Volume of moving object
If capacitor and resistor are integrated within existing structures, then volume is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements the capacitor and resistor within the existing semiconductor device housing and mounting structures, effectively nesting the noise suppression components within the already-present structural framework. This nesting approach minimizes additional volume requirements while the standardized mounting interfaces maintain reasonable manufacturing precision requirements.
Solution Approach 2:
The capacitor and resistor are positioned at specific locations within the device where they can be effectively integrated with existing structures. By selecting optimal placement locations that utilize available space and existing mounting features, the patent achieves compact integration without excessively tightening manufacturing precision requirements across the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively reduces ringing noise in current and voltage between switching element terminals, preventing damage and allowing for a more compact semiconductor device design by integrating the capacitor and resistor within existing terminal or connecting sections without increasing the device size.
Implementation Method 1
a capacitor having an electrostatic capacitance of 1.0 to 8.0 nF
Implementation Method 2
a resistor having a resistance value of 2.0 to 7.0 Ω
Data Source
AI summary
Provided is a semiconductor device including an input terminal including a P terminal and an N terminal; a laminated circuit substrate connected to the input terminal; a power substrate provided above the laminated circuit substrate; a connecting section electrically connecting the laminated circuit substrate and the power substrate; a capacitor provided in a conduction path between the P terminal and the N terminal; and a resistor provided in series with the capacitor in the conduction path between the P terminal and the N terminal. The capacitor may be provided in a region where the input terminal or the connecting section is provided, in an overhead view.