Semiconductor Clock Control via Merged Signal Generation

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Solution Overview

Problem

Existing semiconductor integrated circuit devices with pipeline structures face increased power consumption due to complex control units and separate clock control for each operation unit, especially when clock supply areas are divided into small stages, leading to inefficient power management.

Innovation Solution

A semiconductor integrated circuit device with a process control unit and a clock-control signal generating unit operating in synchronization with the system clock, using clock gating circuits to control clock supply to operation units based on process control signals, allowing for synchronized clock control across multiple operation units with a single clock-control signal generating unit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a separate clock control unit is provided for each operation unit to control clock supply individually, then clock supply control precision is improved, but device complexity increases and power consumption increases

Engineering Contradiction:
Improveclock supply control precisionVSAvoidcontrol unit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Multiple clock control units are merged into a single clock control unit that manages clock supply to multiple operation units. This single unit receives operation start signals and generates appropriate clock control signals for each operation unit, thereby reducing device complexity while maintaining precise clock supply control.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single clock control unit is designed to perform multiple functions by controlling clock supply to different operation units based on received operation start signals. It can selectively enable or disable clock supply to specific operation units (e.g., first operation unit, second operation unit) depending on the processing requirements, achieving universal control capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If clock supply area is divided into small stages for precise control, then clock supply control precision is improved, but power consumption increases

Engineering Contradiction:
Improveclock supply control precisionVSAvoidprocessor power consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The clock control unit employs periodic action by selectively enabling clock supply to operation units only when needed. Based on operation start signals, it activates clock supply to specific operation units during their required processing periods and disables it when not needed, thereby achieving precise control while reducing overall power consumption compared to continuous clock supply to all units.

Inventive Principle:
Principle #19Periodic action

3Measurement precision

If process control unit individually controls each operation unit, then processing control precision is improved, but device complexity increases

Engineering Contradiction:
Improveprocessing control precisionVSAvoidcontrol unit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The control function is segmented between a process control unit that receives operation start signals and a clock control unit that generates clock control signals. This segmentation allows the process control unit to focus on processing control precision while the clock control unit handles clock supply timing, thereby maintaining precise control without excessive complexity in either unit.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8195975B2Semiconductor integrated circuit device and clock control method
Publication Date: 2012.06.05 KK TOSHIBA
  • US8195975B2 patent drawing
  • US8195975B2 patent drawing
  • US8195975B2 patent drawing

AI summary

A plurality of operation units connected in a pipeline structure performs an operation processing on data. A process control unit operates in synchronization with a system clock signal and generates a process control signal for controlling the operation units upon receiving a data notification signal that notifies the process control unit of an arrival of data from outside. A clock-control signal generating unit operates in synchronization with the system clock signal and generates a clock control signal for controlling a clock supply to each of the operation units upon receiving the process control signal.