Semiconductor Clock Domain Control Circuit for Test Efficiency
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Solution Overview
Problem
Existing semiconductor testing methods for large-scale integrated circuits require numerous test patterns or additional terminals, leading to increased test periods, costs, and chip area, as they struggle to efficiently manage clock domains and reduce the number of terminals needed for functional testing.
Innovation Solution
A semiconductor device with a control circuit that selectively supplies a clock signal to predetermined clock domains based on a control signal, allowing for reduced terminal additions and simultaneous testing of multiple clock domains, thereby generating fewer test patterns and reducing the test period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If numerous test patterns are generated for functional testing, then testing coverage is improved, but test period and cost increase
Solution Approach 1:
The patent segments clock domains into groups based on data-path interdependence, allowing independent testing of each group. This segmentation enables parallel test execution and reduces the total number of test patterns needed, thereby shortening the test period while maintaining comprehensive testing coverage.
Solution Approach 2:
The patent dynamically determines the number of scan clock supply terminals to be added based on the extracted data-path interdependence relationships. This dynamic approach optimizes the balance between testing coverage and test efficiency, avoiding both excessive test patterns and insufficient testing.
2Reliability
If numerous test patterns are generated for functional testing, then testing coverage is improved, but test cost increases
Solution Approach 1:
By segmenting clock domains into independent groups based on data-path analysis, the patent reduces the total number of test patterns required. This segmentation strategy directly lowers test cost while preserving comprehensive testing coverage through systematic group-based testing.
Solution Approach 2:
The patent changes the parameter of test pattern quantity by optimizing it based on data-path interdependence relationships. Instead of using a fixed large number of test patterns, the method dynamically determines the optimal number based on circuit characteristics, thereby reducing test cost without compromising coverage.
3Loss of time
If many terminals are added to reduce test patterns, then test period is reduced, but chip area increases
Solution Approach 1:
The patent segments clock domains into groups and adds scan clock supply terminals based on the number of groups rather than the total number of clock domains. This segmentation approach significantly reduces the number of terminals needed compared to adding terminals to each individual clock domain, thereby minimizing chip area occupation while enabling parallel testing to reduce test period.
Solution Approach 2:
The patent makes scan clock supply terminals serve multiple clock domains within the same group simultaneously. This multi-functionality allows a single terminal to control testing for multiple domains, reducing the total number of terminals required and minimizing chip area usage while maintaining efficient test execution.
4Productivity
If many terminals are added to reduce test patterns, then test efficiency is improved, but chip cost increases
Solution Approach 1:
The patent segments clock domains into independent testing groups and adds the minimum necessary scan clock supply terminals based on this segmentation. This approach achieves high test efficiency through parallel group testing while minimizing chip area occupation, thereby reducing chip cost without sacrificing productivity.
Solution Approach 2:
The patent optimizes the parameter of terminal quantity by determining it based on data-path interdependence analysis rather than using a fixed large number. This parameter optimization achieves the right balance between test efficiency and chip area, reducing chip cost while maintaining high productivity.
Data Source
AI summary
A semiconductor device according to an embodiment of the present invention includes: a plurality of clock domains including a plurality of logic circuits operating in accordance with a clock signal; and a control circuit selectively supplying the clock signal to a predetermined number of clock domains selected from the plurality of clock domains based on a control signal.