Semiconductor Device Collector Wiring Layout for Parasitic Inductance Reduction
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Solution Overview
Problem
Heterojunction bipolar transistors (HBTs) used in RF power amplifying circuits face challenges with increased parasitic inductance in collector wiring lines, particularly when transistor cells are arranged in multiple columns with collector pads located at one end, leading to inefficiencies and heat management issues.
Innovation Solution
A semiconductor device design featuring two rows of transistor cells with collector extended wiring lines intersecting each other, a collector integrated wiring line connecting these lines, and an emitter wiring line disposed between collector and base extended wiring lines to reduce parasitic inductance and enhance heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a pad for collectors is disposed near one end portions of four cell columns, then the device complexity is reduced, but the parasitic inductance of the collector wiring line increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration, placing transistor cells in multiple layers above the substrate. This vertical stacking allows collector wiring lines to connect to collectors in different layers at different positions, reducing the total wire length and parasitic inductance while maintaining a compact footprint.
Solution Approach 2:
The patent implements a nested structure where transistor cells are stacked vertically, with lower-layer cells positioned beneath upper-layer cells. The collector wiring lines are routed to connect to collectors at different vertical levels, creating a nested connection pattern that minimizes wire length and parasitic inductance.
2Power
If transistor cells are arranged in four cell columns, then the output power is increased, but the parasitic inductance of the collector wiring line increases
Solution Approach 1:
The patent arranges transistor cells in a three-dimensional stacked configuration rather than a planar four-column layout. This vertical arrangement allows for increased power output through more cells while keeping collector wiring lines shorter by connecting to collectors at different vertical positions, thereby reducing parasitic inductance.
Solution Approach 2:
The patent divides the transistor cell array into multiple stacked layers, with each layer containing fewer cells arranged in a compact pattern. This segmentation allows collector wiring lines to access collectors in different layers at different horizontal positions, reducing the overall wire length and parasitic inductance compared to a single-plane four-column arrangement.
Data Source
AI summary
A semiconductor device includes two cell rows, each of which is formed of a plurality of transistor cells aligned in parallel to each other. Each of the plurality of transistor cells includes a collector region, a base region, and an emitter region that are disposed above a substrate. A plurality of collector extended wiring lines are each connected to the collector region of a corresponding one of the plurality of transistor cells and are extended in a direction intersecting an alignment direction of the plurality of transistor cells. A collector integrated wiring line connects the plurality of collector extended wiring lines to each other. A collector intermediate integrated wiring line that is disposed between the two cell rows in plan view connects the plurality of collector extended wring lines extended from the plurality of transistor cells that belong to one of the two cell rows to each other.