Semiconductor Packaging Structure with Colloid Protection

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Solution Overview

Problem

The existing semiconductor chip packaging process using a temporary glass carrier poses a risk of damaging the chip during removal, making the chip vulnerable to damage.

Innovation Solution

A semiconductor packaging structure is developed with a conductive layer and a colloid that spaces the chip from the conductive layer, using a copper-tin eutectic layer for electrical connection and a colloid to cover the chip, preventing exposure and potential damage, and employing a method involving temporary carriers and a metal frame for secure handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a temporary glass carrier is used to support and position the semiconductor chip during packaging, then the chip can be securely held and positioned, but the removal of the carrier exposes the back face of the chip making it vulnerable to damage

Engineering Contradiction:
Improvechip positioning and handlingVSAvoidchip integrity
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a protective colloid coating on the chip back face before the temporary carrier is removed. This pre-established protective layer ensures the chip is already protected when the carrier is taken off, eliminating the vulnerability period where the back face would be exposed and susceptible to damage during carrier removal.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The colloid coating acts as an intermediary protective layer between the chip back face and the external environment. This intermediate substance provides mechanical protection and isolation, allowing the chip to be handled and the carrier to be removed without direct exposure of the fragile chip back face to potential damage sources.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the chip is directly exposed after carrier removal, then the packaging process can be completed, but the chip becomes vulnerable to damage

Engineering Contradiction:
Improvepackaging process efficiencyVSAvoidchip damage risk
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The protective colloid coating is applied to the chip back face before carrier removal, ensuring protection is already in place before the chip becomes exposed. This preliminary protective measure allows the chip to be exposed during subsequent packaging operations without creating vulnerability, thus maintaining productivity while eliminating damage risk.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The colloid coating provides beforehand cushioning by creating a protective barrier on the chip back face prior to any potential damage occurring. This pre-established protective layer absorbs or distributes mechanical stresses and protects the chip during handling and packaging operations, preventing damage while allowing efficient processing.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively prevents chip damage by maintaining a gap between the chip and the conductive layer, ensuring secure packaging and reducing scrap rates due to breakage, while allowing for stable microstructure formation and efficient packaging processes.

Implementation Method 1

The electrical conductor 10 includes a copper-tin eutectic layer, which reduces a temperature for forming the electrical conductor 10 and increases the stability of microstructures of the electrical conductor 10.

Methodology Applied
Scientific EffectMetallurgical bonding: Welding

Data Source

PatentUS11569195B2Semiconductor packaging structure and method of fabricating same
Publication Date: 2023.01.31 KORE SEMICONDUCTOR INC
  • US11569195B2 patent drawing
  • US11569195B2 patent drawing
  • US11569195B2 patent drawing

AI summary

A semiconductor packaging structure manufactured in a manner which does not leave the chip damaged or susceptible to damage upon the removal of temporary manufacturing supports includes at least one electrical conductor, at least one conductive layer, a chip, and a colloid. The chip is spaced from the conductive layer, the electrical conductor is disposed between the conductive layer and the chip and electrically connects the conductive layer to the chip. The colloid covers all outer surfaces of the chip. A method of fabricating such a semiconductor packaging structure is also provided.