3D Semiconductor Memory with Concave Buffer Layer
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited by the cost and complexity of fine pattern forming technologies, which restricts their ability to increase memory density, while three-dimensional devices offer a potential solution but face challenges in maintaining reliability due to etching processes that can deteriorate electric characteristics.
Innovation Solution
A semiconductor device with a substrate, electrode structure, and semiconductor patterns where the upper pattern has a gap-filling portion and sidewall portion extending from it, and a lower pattern with a concave top surface, filled by alternating sacrificial and insulating layers, and processed through specific etching and thermal treatments to prevent excessive etching and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional memory devices are fabricated using conventional etching processes, then memory density and integration are improved, but electric characteristics deteriorate due to excessive etching
Solution Approach 1:
A lower semiconductor pattern with a concave top surface is formed in advance before forming the upper semiconductor pattern. This preliminary structure serves as a buffer that prevents the upper pattern from being excessively etched during subsequent etching processes, thereby protecting electric characteristics while allowing high-density three-dimensional integration
Solution Approach 2:
The lower semiconductor pattern acts as a cushioning layer that absorbs excessive etching damage before it reaches the upper semiconductor pattern. This protective buffer structure ensures that even if etching conditions are not perfectly controlled, the critical upper pattern maintaining electric characteristics is protected from damage
2Productivity
If two-dimensional semiconductor memory devices use fine pattern forming technology to increase integration, then memory density is improved, but process cost and complexity increase significantly
Solution Approach 1:
The invention transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. By stacking electrode structures and semiconductor patterns in the vertical dimension, memory density is increased without requiring finer lateral patterning, thus avoiding the cost and complexity penalties of advanced fine pattern forming technologies
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the reliability of three-dimensional semiconductor devices by preventing excessive etching and maintaining electric characteristics, thus enhancing the integration and performance of memory devices.
Implementation Method 1
performing a thermal treatment process, after the first etching process
Data Source
AI summary
A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.