Conductive and Insulating Layer Formation for Semiconductor Interconnects
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in achieving smaller, higher-density semiconductor devices with improved electrical interconnection and packaging, which are essential for reducing power consumption and increasing performance while minimizing device footprint.
Innovation Solution
The method involves forming conductive and insulating layers on semiconductor devices and packages by depositing and heating conductive materials like silver, platinum, and copper, and using isolating materials such as dielectric ink and thermosetting resin, while also treating interconnect structures with hydrophilic plasma and deflashing processes to enhance dispersion and adhesion, allowing for the creation of smaller, more efficient semiconductor devices with reduced warpage and cost-effective packaging solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional semiconductor manufacturing processes are used, then manufacturing experience and established processes are available, but achieving smaller, higher-density devices with improved electrical interconnection and packaging is difficult
Solution Approach 1:
The manufacturing process is divided into distinct stages: screen printing conductive paste, firing to form conductive layers, forming insulating layers, and creating vias. This segmentation allows each process step to be optimized independently, enabling higher density and better interconnection while managing overall process complexity
Solution Approach 2:
The patent modifies material parameters by using specific conductive paste compositions and insulating layer materials with controlled properties. By changing material parameters rather than fundamental process approaches, the patent achieves improved device density and interconnection quality within existing manufacturing frameworks
2Volume of moving object
If device size is reduced to achieve smaller footprint, then power consumption decreases and performance increases, but manufacturing precision and interconnection quality become more challenging
Solution Approach 1:
The patent applies different material compositions and processing conditions to different regions of the device. Conductive paste is selectively applied to specific areas, and insulating layers are formed with varying properties in different zones. This local quality approach enables precise interconnections in miniaturized devices while maintaining overall manufacturing feasibility
Solution Approach 2:
Conductive layers are formed through screen printing and firing before final device assembly. This preliminary formation of conductive pathways ensures that interconnection quality is established early in the manufacturing process, allowing subsequent steps to focus on device integration rather than creating connections in already-miniaturized structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of smaller, higher-density semiconductor devices with improved electrical interconnects and packaging, reducing power consumption and increasing performance while minimizing device size and cost, and achieving moderate warpage and fine pitch interconnects through direct writing processes like inkjet and screen printing.
Implementation Method 1
heating the first conductive material from the first state to a second state, where the second state is different from the first state
Implementation Method 2
treating interconnect structures with hydrophilic plasma and deflashing processes to enhance dispersion and adhesion
Data Source
AI summary
Methods of forming conductive and insulating layers for semiconductor devices and packages. Substrate is provided with integrated circuit device and interconnect structure mounted thereon, the interconnect structure adjacent the integrated circuit device. The integrated circuit device and portions of the interconnect structure can be covered with an encapsulation exposing a portion of the interconnect structure. Conductive material is formed over the exposed portion of the interconnect structure by a depositing process followed by a heating process to alter the chemical properties of the conductive material. Optionally, a dispersing process may be incorporated.