Semiconductor Device Conductive Pillars Vertical Resistance
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Solution Overview
Problem
Existing stacked type semiconductor memory devices face challenges in achieving high resistance values per unit surface area due to the limitations in current path design and manufacturing processes, leading to larger device sizes and increased complexity.
Innovation Solution
The semiconductor device incorporates conductive pillars extending in the Z-direction, formed within stacked bodies that also house memory cell transistors, allowing for a high resistance value per unit surface area by utilizing the same process as memory cell transistor arrangement, and connecting these pillars in series to achieve desired resistance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional current path design is used in stacked type semiconductor memory devices, then device size increases and manufacturing complexity increases, but resistance value per unit surface area cannot be sufficiently improved
Solution Approach 1:
The patent transitions from planar current paths to three-dimensional vertical current paths by extending conductive paths through the stacked body structure. Conductive pillars are formed to pierce through multiple insulating films and electrode films in the stacking direction, enabling current to flow vertically through the stacked layers rather than laterally across the substrate surface. This dimensional change achieves high resistance values within a compact footprint.
Solution Approach 2:
The patent implements a nested structure where conductive pillars are positioned within and extend through the stacked body, which itself is nested on the semiconductor substrate. The stacked body contains alternating layers of insulating films and electrode films, with the conductive pillars penetrating through these nested layers to establish vertical current paths that pass through multiple functional layers.
2Manufacturing precision
If separate manufacturing processes are used for resistor regions, then manufacturing complexity increases and process costs increase, but resistance values can be achieved
Solution Approach 1:
The patent merges the resistor formation process with the memory cell transistor formation process by using the same stacked body structure and the same manufacturing steps for both. The conductive pillars that form the current paths for resistors are formed using identical processes as those forming current paths for memory cell transistors, including the same film deposition, patterning, and etching steps. This eliminates the need for separate resistor region manufacturing processes.
Solution Approach 2:
The stacked body structure serves multiple functions simultaneously: it provides the insulating and conductive layers for memory cell transistors, and it provides the same layers as the resistor current paths. The conductive pillars serve dual purposes by functioning as both memory cell transistor current paths and resistor current paths, depending on their specific configuration and connection within the stacked body.
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate, a first portion and a second portion of an upper layer portion of the semiconductor substrate being conductive; an insulating member electrically isolating the first portion from the second portion; a first stacked body provided in a region directly above the second portion, the first stacked body including first insulating films and electrode films stacked alternately; a semiconductor pillar provided inside the first stacked body and extending in a stacking direction; a charge storage film provided between the semiconductor pillar and the electrode films; a second stacked body provided in a region directly above the first portion, the second stacked body including second insulating films and third insulating films stacked alternately; and two first conductive pillars provided inside the second stacked body extending in the stacking direction, lower ends thereof being connected to the first portion.