Semiconductor Package Conductive Wall Capacitance Density

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Solution Overview

Problem

Current semiconductor package devices face challenges in achieving high capacitance density while maintaining a compact size, as existing designs often require increased layout space for conductive contacts, which can complicate circuit design and increase thickness.

Innovation Solution

The semiconductor package device incorporates a structure with a conductive layer, a semiconductor wall, a conductive wall, and an insulation layer, where the conductive walls are separated by the insulation layer, allowing for efficient capacitance distribution without the need for extensive conductive contact layout, thereby optimizing capacitance density within a reduced footprint.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If existing capacitor designs are used to achieve high capacitance density, then capacitance per area may be improved, but the layout space for conductive contacts increases and device thickness increases

Engineering Contradiction:
Improvecapacitance densityVSAvoidlayout space for conductive contacts
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent transitions from planar conductive contact layouts to three-dimensional vertical conductive walls. The conductive walls extend vertically from the first conductive layer through the insulation layer to the second conductive layer, utilizing the vertical dimension to provide conductive pathways without requiring additional horizontal layout space. This dimensional change resolves the contradiction by maintaining capacitance density while eliminating the need for extensive conductive contact area in the planar domain.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where the semiconductor wall is positioned within the space defined by the conductive walls and insulation layer. The conductive walls are embedded within the insulation layer, creating a compact nested arrangement. This nesting allows multiple functional elements (conductive walls, insulation layer, semiconductor wall) to occupy overlapping spatial volumes, thereby achieving high capacitance density without increasing the horizontal footprint.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If existing capacitor designs are used to achieve high capacitance density, then capacitance per area may be improved, but device thickness increases

Engineering Contradiction:
Improvecapacitance densityVSAvoiddevice thickness
Core Design Contradiction:
Quantity of substanceVSLength of stationary object

Solution Approach 1:

The patent applies local quality by creating distinct functional regions with specific properties: the semiconductor wall provides high-k dielectric properties in specific locations, the conductive walls provide localized conductive pathways, and the insulation layer provides electrical isolation where needed. This localized functional differentiation allows the capacitor to achieve high capacitance density through optimized local structures rather than uniformly increasing overall device thickness.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent utilizes the vertical dimension efficiently by stacking conductive layers, insulation layers, and semiconductor walls in a compact vertical arrangement. The conductive walls extend vertically to connect conductive layers without requiring excessive vertical spacing, and the overall structure is designed to maximize capacitance per unit volume while maintaining a controlled thickness profile that does not excessively increase device height.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If conductive walls are separated by insulation layer to optimize capacitance distribution, then capacitance density is improved, but structural complexity increases

Engineering Contradiction:
Improvecapacitance distributionVSAvoidstructural complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments the capacitor structure into distinct functional modules: first conductive layer, semiconductor wall, first conductive wall, insulation layer, and second conductive layer. Each segment performs a specific function (conduction, dielectric, insulation) and can be independently formed and optimized. This segmentation allows for improved capacitance distribution through controlled electrical isolation while managing structural complexity by creating repeatable, modular units that can be systematically assembled.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances capacitance density without increasing the device's thickness, simplifying circuit design and improving performance in compact electronic products.

Implementation Method 1

an insulation layer disposed on the first conductive layer and between the semiconductor wall and the first conductive wall

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Implementation Method 2

Capacitors are passive components used in various electronic products, which go along with the trend of miniaturization

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11107881B2Semiconductor package devices having conductive layer, semiconductor wall, conductive wall, and insulation layer
Publication Date: 2021.08.31 ADVANCED SEMICON ENG INC
  • US11107881B2 patent drawing
  • US11107881B2 patent drawing
  • US11107881B2 patent drawing

AI summary

The subject application relates to a semiconductor package device, which includes a first conductive layer; a semiconductor wall disposed on the first conductive layer; a first conductive wall disposed on the first conductive layer; and an insulation layer disposed on the first conductive layer and between the semiconductor wall and the first conductive wall.