Semiconductor Conductor Plate Arrangement for Inductance Reduction
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Solution Overview
Problem
Existing semiconductor devices for power conversion struggle to sufficiently reduce inductance, particularly in three-level inverter circuits, due to limited overlap width between terminals, which affects efficiency and cost.
Innovation Solution
A semiconductor device design featuring an insulating substrate with at least four semiconductor elements, a base plate, and conductor plates where the positive and negative conductor plates face an intermediate potential conductor plate, increasing the overlap area and reducing inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the U terminal and M terminal are arranged close to each other to reduce inductance, then the wiring inductance is reduced, but the overlap width between terminals is narrow which limits the inductance reduction effect
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of terminals to a three-dimensional stacked configuration where conductor plates are arranged in multiple layers. The first and second conductor plates are positioned at different heights (different Z-dimension) facing each other, creating a multi-dimensional current path that significantly increases the effective overlap area while maintaining compact terminal spacing, thereby resolving the contradiction between reducing inductance and maintaining sufficient overlap width
Solution Approach 2:
The patent employs a nested structure where conductor plates are arranged in concentric or layered configurations. The first conductor plate is positioned centrally with the second conductor plate surrounding or adjacent to it in the vertical direction, creating a nested arrangement that maximizes the overlapping area between opposite-polarity conductors within a compact footprint, effectively increasing the inductance reduction effect without requiring larger terminal spacing
2Loss of energy
If the terminal arrangement is optimized for three-level mode operation, then inductance is reduced for three-level operation, but bouncing voltage increases when switching to two-level mode
Solution Approach 1:
The patent designs a terminal arrangement and conductor plate configuration that serves multiple operational modes. The symmetric arrangement of first and second conductor plates with opposite polarities facing each other creates a balanced structure that provides low inductance for three-level operation while also maintaining controlled impedance characteristics for two-level operation, enabling the same physical structure to universally support both operating modes without excessive bouncing voltage
Solution Approach 2:
The patent employs asymmetric positioning of the third conductor plate relative to the first and second plates. The third plate is offset from the central axis, creating an asymmetric current distribution that helps balance the inductance values for different switching modes, thereby reducing bouncing voltage during mode transitions while maintaining optimal performance for both three-level and two-level operations
Data Source
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AI summary
Provided is a semiconductor device in which an intermediate potential conductor plate faces a positive conductor plate and a negative conductor plate in order to reliably reduce inductance. The semiconductor device includes: an insulating substrate (11) on which at least four semiconductor elements forming a three-level power conversion circuit are mounted; a base plate (3) on which the insulating substrate is provided; a positive conductor plate (21) with a positive DC potential which is connected to one semiconductor element among the semiconductor elements; a negative conductor plate (22) with a negative DC potential which is connected to another semiconductor element among the semiconductor elements; and an intermediate potential conductor plate (23) with an intermediate potential which is connected to the remaining two semiconductor elements among the semiconductor elements. The positive conductor plate, the negative conductor plate, and the intermediate potential conductor plate are provided on the base plate. The positive conductor plate and the negative conductor plate are arranged close to the intermediate potential conductor plate so as to face the intermediate potential conductor plate.