Semiconductor Conductor Post Asymmetric Insulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The linear thermal expansion coefficient mismatch between semiconductor chips and wiring boards leads to stress on conductor posts, particularly at the chip's corners, causing peeling issues when the insulating layer's temperature exceeds its softening point, and existing solutions struggle to balance stress relaxation with coupling reliability and pitch between conductor posts.
Innovation Solution
The design involves an overlapped region between conductor posts and insulating films, where the width closer to the chip's center is smaller than further away, with the conductor post's center shifted towards the periphery, allowing for stress relaxation while maintaining coupling reliability by adjusting the pitch and overlap angles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If the insulating layer is made to run over the periphery of the electrode and the conductor post periphery is made to run over the insulating layer to increase the run-over amount, then stress applied to the conductor post is relaxed, but the diameter of the conductor post must be made large or the opening for exposing the electrode must be made small, which causes adjacent conductor posts to be short-circuited via solder or increases coupling resistance
Solution Approach 1:
The patent applies different run-over amounts of the insulating layer at different locations: a first run-over amount at the first end of the conductor post and a second run-over amount at the second end, where the first run-over amount is larger than the second run-over amount. This local differentiation allows stress relaxation at the high-stress end while maintaining proper coupling and avoiding short-circuits at the other end
Solution Approach 2:
The insulating layer's run-over structure is made asymmetric with respect to the conductor post, with unequal run-over amounts at opposite ends. This asymmetric configuration optimizes stress distribution and prevents both short-circuits and excessive coupling resistance by providing different levels of stress relaxation where needed
2Stress or pressure
If the diameter of the conductor post is made large to increase the run-over amount of the insulating layer, then stress relaxation is improved, but the pitch of the conductor posts becomes small, causing adjacent conductor posts to be short-circuited via solder
Solution Approach 1:
Instead of uniformly increasing conductor post diameter, the patent locally increases the insulating layer run-over amount at specific ends of conductor posts where stress is highest, achieving stress relaxation without requiring larger post diameters that would reduce pitch and cause short-circuits
3Stress or pressure
If the opening for exposing the electrode is made small to increase the run-over amount of the insulating layer, then stress relaxation is improved, but coupling resistance between the conductor post and the electrode becomes large
Solution Approach 1:
The patent applies the insulating layer run-over selectively at specific ends of conductor posts rather than uniformly, allowing stress relaxation at the end with larger run-over while maintaining adequate opening size and low coupling resistance at the end with smaller run-over
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces stress on conductor posts, preventing peeling and ensuring reliable coupling between the semiconductor chip and wiring board across varying temperatures.
Implementation Method 1
The linear thermal expansion coefficient of a semiconductor chip differs from the linear thermal expansion coefficient of a wiring board in a plane direction horizontal to the wiring board. Therefore, when a temperature change occurs in a semiconductor device, stress is produced in a shear direction at the interface between the semiconductor chip and the wiring board.
Data Source
AI summary
A semiconductor chip and a wiring board are coupled to each other through conductor posts. The centers of conductor posts situated above openings at the outermost periphery shift from the centers of the openings in a direction away from the center of the semiconductor chip. When a region where each of the conductor posts and an insulating layer are overlapped with each other is designated as an overlapped region, the width of the overlapped region more on the inner side than the opening is smaller than the width of the overlapped region more on the outer side than the opening. Thus, while stress applied to the conductor posts is relaxed, coupling reliability between the semiconductor chip and the wiring board is retained.