Semiconductor Package Connection Structure with Asymmetric Width for Thermal Stress Management
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Solution Overview
Problem
Semiconductor device packages face reliability issues due to coefficient of thermal expansion (CTE) mismatch between materials, leading to delamination during thermal cycles, which affects the package's performance and reliability.
Innovation Solution
A semiconductor device package design featuring a connection structure with two portions of different widths, where the wider portion acts as a support and the narrower portion is separated from the dielectric layer by a space, mitigating tensile stress and preventing delamination by acting as a buffer during thermal cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If hybrid bonding technique is used to form semiconductor device package, then bonding strength is improved, but delamination occurs due to CTE mismatch during thermal cycles
Solution Approach 1:
The connection structure is divided into two portions with different widths: a first portion that bonds to the dielectric layer and a second portion with smaller cross-sectional area. This segmentation allows the structure to accommodate differential thermal expansion while maintaining bonding integrity, as the narrower second portion can flex independently to relieve stress from CTE mismatch.
Solution Approach 2:
Different portions of the connection structure have different geometric properties - the first portion has larger cross-sectional area for strong bonding, while the second portion has smaller cross-sectional area for stress accommodation. This local variation in geometry optimizes both bonding strength and delamination resistance in different regions of the same structure.
2Strength
If dielectric layer is formed to surround connection structure, then structural support is improved, but tensile stress increases during thermal expansion
Solution Approach 1:
The connection structure is segmented into portions with different cross-sectional areas, allowing the dielectric layer to provide structural support to the wider first portion while the narrower second portion can expand independently, reducing tensile stress concentration at the dielectric connection interface during thermal cycles.
3Ease of manufacture
If connection structure has uniform width, then manufacturing simplicity is improved, but stress concentration occurs at dielectric interface during thermal cycles
Solution Approach 1:
The connection structure transitions from a uniform width design to an asymmetric design where the second portion has a smaller cross-sectional area than the first portion. This asymmetric geometry is specifically designed to reduce stress concentration at the dielectric interface during thermal expansion, while remaining compatible with standard manufacturing processes like electroplating.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces delamination risks and enhances the reliability of semiconductor device packages by managing thermal expansion stresses through the use of a space as a buffer and a wider support structure within the connection structure.
Implementation Method 1
coefficient of thermal expansion (CTE) mismatch of two or more materials during or subsequent to thermal cycle(s) may result in delamination issue
Data Source
AI summary
A semiconductor device package includes a connection structure having a first portion and a second portion extending from the first portion, the second portion having a width less than the first portion; and a dielectric layer surrounding the connection structure, wherein the dielectric layer and the second portion of the connection structure defines a space.