Semiconductor Contact Structure for Alignment Precision
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Solution Overview
Problem
In semiconductor devices with miniaturized features, the narrow spacing between adjacent gate structures leads to misalignment issues during the fabrication of self-aligned contacts, resulting in increased contact resistance due to reduced contact areas.
Innovation Solution
A semiconductor device structure featuring gate electrodes with spacers and contact structures where the contact's bottom is in indirect contact with the outer sidewall of the spacers, and a method involving a substrate with fin-shaped protrusions, gate stacks, sacrificial material replacement with interlayer dielectric, and subsequent contact formation to ensure accurate alignment and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned contacts are used to maintain alignment in narrow spaces, then manufacturing precision is improved, but contact resistance increases due to lateral shift and reduced contact area
Solution Approach 1:
The patent introduces a vertical dimension solution by forming a contact structure that extends downward to directly contact the active region, rather than relying solely on horizontal alignment. The contact structure penetrates through the interlayer dielectric layer to establish vertical electrical connection, transforming the alignment problem from a 2D lateral positioning issue into a 3D vertical connection solution that is less sensitive to lateral misalignment.
Solution Approach 2:
The patent performs preliminary actions by first forming the interlayer dielectric layer with specific material composition and properties before contact formation. The interlayer dielectric layer is prepared with controlled refractive index and material composition to facilitate subsequent contact etching and alignment, ensuring optimal conditions are established in advance for accurate contact placement despite narrow spacing constraints.
2Productivity
If feature size is continuously miniaturized to increase integration density, then productivity is improved, but manufacturing precision deteriorates due to severe misalignment in narrow spaces
Solution Approach 1:
The patent addresses miniaturization challenges by transitioning to vertical contact structures that extend through the interlayer dielectric to contact the active region directly. This vertical approach reduces dependency on lateral alignment precision, enabling continued feature size reduction and integration density improvement without proportionally decreasing manufacturing precision.
Solution Approach 2:
The patent changes material parameters by selecting interlayer dielectric materials with specific refractive indices and composition ratios (e.g., silicon oxide with nitrogen content 5-50 at%, or silicon oxynitride). These parameter changes optimize the etching characteristics and alignment properties during contact formation, maintaining manufacturing precision even as feature sizes are miniaturized for higher integration density.
Data Source
AI summary
A semiconductor device includes a substrate, gate electrodes, spacers and contact structures. The gate electrodes are disposed on the substrate, and the spacers are disposed on the sidewalls of the gate electrodes. Each of the spacers has an inner sidewall and an outer sidewall. The contact structure is disposed between the gate electrodes, and its bottom is in direct contact with all the region of the outer sidewall of the spacers.