Semiconductor Contact Formation Using Segmented Etch Stop Layers
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in forming precise metal gates and contact plugs due to limitations in photoresist and lithography methods, leading to position shifts and electrical performance issues in nanometer-scale devices.
Innovation Solution
A method is developed to form semiconductor devices by using a contact etching stop layer and capping layer as stop layers to create separate source/drain and gate structure contact openings, allowing for precise exposure and removal to form direct connections between source/drain regions and metal gates, thereby improving the integrated process and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If current photoresist and lithography techniques are used to form metal gate and contact plug, then the manufacturing process can be maintained, but position shift of contact plug occurs and electrical performance deteriorates
Solution Approach 1:
The patent segments the contact formation process into two separate etching operations: first etching source/drain contact openings through the CESL to expose source/drain regions, then etching gate contact openings through the capping layer to expose the metal gate. This segmentation prevents position shifts by establishing distinct reference frames for each contact type, thereby improving manufacturing precision and electrical performance.
Solution Approach 2:
The patent introduces two intermediary stop layers: the contact etching stop layer (CESL) between the source/drain regions and the overlying dielectric layers, and the capping layer between the metal gate and the interlayer dielectric. These intermediary layers serve as precise etching boundaries that enable accurate contact opening formation without penetrating into the underlying functional regions, thus improving contact plug positioning accuracy.
2Productivity
If contact openings are formed simultaneously for source/drain and metal gate, then process steps are reduced, but position accuracy deteriorates due to lithography limitations
Solution Approach 1:
The patent divides the contact opening formation into sequential steps: first forming source/drain contact openings by etching through the CESL, then forming gate contact openings by etching through the capping layer. This segmentation allows each contact type to be positioned with high accuracy using its own reference frame, overcoming lithography limitations while maintaining overall process efficiency.
Solution Approach 2:
The patent performs preliminary actions by forming the CESL and capping layers before contact opening etching. These stop layers are prepared in advance with precise positioning, enabling subsequent etching operations to achieve high accuracy without requiring complex lithography alignment. The stop layers serve as pre-established reference structures that guide the contact opening formation.
3Device complexity
If a single etching process is used for all contact openings, then process complexity is reduced, but selective removal of different layers becomes difficult
Solution Approach 1:
The patent applies local quality by giving different regions different stop layer structures: the CESL is positioned over source/drain regions while the capping layer is positioned over the metal gate. This allows selective etching where the CESL protects source/drain regions during gate contact formation, and the capping layer protects the metal gate during source/drain contact formation, enabling precise selective layer removal.
Solution Approach 2:
The patent utilizes parameter changes by employing different etching selectivities for the CESL and capping layer. The etching process parameters are optimized to etch through the CESL without significantly affecting the capping layer, and vice versa. This parameter differentiation enables selective removal of the appropriate stop layer for each contact type while maintaining process simplicity.
Data Source
AI summary
A method of forming a semiconductor device includes following steps. Firstly, a gate structure is formed on a substrate, and two source/drain regions are formed. Then, a contact etching stop layer (CESL) is formed to cover the source/drain regions, and a first interlayer dielectric (ILD) layer is formed on the CESL. Next, a replace metal gate process is performed to form a metal gate and a capping layer on the metal gate, and a second ILD layer is formed on the first ILD layer. Following these, a first opening is formed in the second and first ILD layers to partially expose the CESL, and a second opening is formed in the second ILD to expose the capping layer. Finally, the CESL and the capping layer are simultaneously removed.