Semiconductor Contact Layout for Mixed-Voltage Etch Control
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Solution Overview
Problem
The semiconductor industry faces challenges in forming contacts for low-voltage and high-voltage semiconductor devices with existing technologies, which often result in device defects and increased costs due to over-etching and the need for multiple masking steps.
Innovation Solution
The method involves forming low-voltage and high-voltage semiconductor devices in separate regions of a substrate with gates of varying heights, using patterned photoresists to create openings of different widths to expose source/drain regions and gates without over-etching, thereby reducing device defects and eliminating the need for additional masking steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form contacts for low-voltage and high-voltage semiconductor devices, then contacts can be formed, but over-etching occurs resulting in device defects
Solution Approach 1:
The patent segments the contact formation process by creating separate opening regions for low-voltage and high-voltage devices. Different opening widths are defined in the patterned photoresist layer: a first opening width for low-voltage devices and a second opening width for high-voltage devices. This segmentation allows selective etching to different depths without over-etching, as each opening width is optimized for its respective device type, thereby preventing device defects while maintaining manufacturing precision.
2Manufacturing precision
If multiple masking steps are used to form contacts for different device types, then precise contact formation is achieved, but manufacturing complexity and costs increase
Solution Approach 1:
The patent merges multiple masking operations into a single masking step. A patterned photoresist layer is formed that simultaneously defines both the first opening regions for low-voltage devices and the second opening regions for high-voltage devices. This single patterned layer serves as a mask for etching both types of contacts in one process sequence, eliminating the need for separate masking steps while maintaining the precision required for different contact formations, thus reducing manufacturing complexity.
3Ease of manufacture
If uniform opening widths are used for all contacts, then the masking process is simplified, but over-etching occurs in high-voltage regions
Solution Approach 1:
The patent applies local quality by varying the opening widths in different regions of the patterned photoresist layer. The first opening width is optimized for low-voltage device contacts, while the second opening width is optimized for high-voltage device contacts. This local variation in opening dimensions allows the etching process to achieve appropriate depths for each device type without over-etching, maintaining manufacturing precision while still using a single masking layer for ease of manufacture.
Data Source
AI summary
Methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. In an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ILD over the first gate and the second gate; a first contact extending through the ILD and coupled to the first source/drain region; and a second contact extending through the ILD, coupled to the second source/drain region, and having a width greater a width of the first contact and a height greater than a height of the first contact.