Semiconductor Contact Formation via Selective Fill Removal
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Solution Overview
Problem
The reduction in contact critical dimension in semiconductor manufacturing poses challenges such as open contact risk, difficulty in scaling contact CD, poor connection between the active area and gate due to thick resist or overlay variations, and increased leakage from the top of the gate, along with challenges in controlling contact resistance and interlayer dielectric deposition.
Innovation Solution
A method involving a substrate with a first interlayer dielectric having a first opening to expose the active area surface, filled with a selectively removable fill material, followed by a second interlayer dielectric with larger openings to expose the fill material, which is then removed and filled with a conductive material to form a contact, reducing the aspect ratio and improving process control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thick resist is used for contact hole etching, then the etching process can be completed, but the contact critical dimension cannot be scaled down and open contact risk increases
Solution Approach 1:
The contact formation process is segmented into multiple stages: first forming a contact hole through the first interlayer dielectric to expose the active area, then filling with conductive material, and finally forming a second interlayer dielectric with openings for additional contacts. This segmentation allows each stage to be optimized independently, enabling contact CD scaling while managing process complexity.
Solution Approach 2:
The patent introduces a vertical stacking dimension by forming multiple interlayer dielectric layers (first and second interlayer dielectrics) with different opening patterns. This multi-layer approach allows contact holes to be formed at different depths and positions, enabling fine control of contact critical dimensions while avoiding the limitations of single-layer thick resist processes.
2Area of moving object
If the contact critical dimension is reduced, then higher integration is achieved, but open contact risk and manufacturing challenges increase
Solution Approach 1:
The patent applies different dielectric materials with distinct etch selectivities to different regions (first interlayer dielectric vs. second interlayer dielectric). This allows precise local control of the etching process, enabling formation of small contact holes with well-defined boundaries while maintaining overall contact reliability through material property optimization.
Solution Approach 2:
The patent changes the etch selectivity parameter by using different dielectric materials that exhibit different etching rates and characteristics. This parameter change enables precise control of contact hole dimensions and shapes, allowing reliable formation of small contact holes while managing the risks associated with reduced contact critical dimensions.
3Length of stationary object
If a high aspect ratio contact hole is formed, then deep contacts are achieved, but metal CVD process control and resistance consistency become difficult
Solution Approach 1:
The contact formation is segmented into multiple shallower holes formed in separate dielectric layers rather than one deep hole. This segmentation reduces the aspect ratio of each individual contact hole, making metal CVD filling more controllable and resistance more consistent, while still achieving the required electrical connection through the stacked structure.
Solution Approach 2:
The patent distributes the contact depth requirement across multiple vertical layers (first and second interlayer dielectrics), transforming a single deep contact problem into multiple shallower contacts. This dimensional redistribution reduces the aspect ratio of each contact hole, improving metal deposition control and resistance consistency.
4Quantity of substance
If interlayer dielectric deposition is performed with small process window, then thin films are deposited, but void formation occurs
Solution Approach 1:
The patent changes the material composition parameter of the interlayer dielectric to achieve different etch selectivities. This material parameter change allows optimization of the deposition process window, enabling formation of thin films without voids by selecting dielectric materials that provide adequate process margins while maintaining the required film thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for precise control of contact resistance, reduces void formation, and simplifies metal deposition, while minimizing spacer etching and leakage, enabling the contact CD to be easily scaled to a desired target value.
Implementation Method 1
The first opening is filled with a fill material, that can be selectively removed with respect to the material of the first interlayer dielectric
Implementation Method 2
the first opening and the second opening are filled with a conductive material to form a contact
Implementation Method 3
The exposed portion of the surface of the active area can be formed with silicide
Data Source
AI summary
A semiconductor device and method for manufacturing the same are provided. A substrate with an active area and a first interlayer dielectric formed over the substrate is provided. The first interlayer dielectric has a first opening exposing a portion of a surface of the active area, the first opening being filled with a fill material. A second interlayer dielectric is formed over the first interlayer dielectric with a second opening substantially exposing an upper portion of the fill material in the corresponding first opening. The fill material is then removed and the first opening and the second opening are filled with a conductive material to form a contact.