Semiconductor Contact Layout for GIDL-Safe Device Scaling
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Solution Overview
Problem
The shrinking of semiconductor device size is limited by the need to maintain adequate spacing to prevent gate induced drain leakage (GIDL) due to band-to-band tunneling, which increases basal voltage and limits the process of size reduction.
Innovation Solution
A semiconductor device design with a conductive contact disposed between first and second conductive type doped regions, electrically isolated by isolators, and a conductive contact material filled in a recess to reduce parasitic substrate resistance and improve current conduction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If appropriate spaces are maintained between internal elements to prevent GIDL, then leakage current accumulation is prevented, but the size of the semiconductor device cannot be shrunk further
Solution Approach 1:
A conductive contact is introduced as an intermediary element between the first conductive type doped region and the second conductive type doped region. This conductive contact provides a controlled electrical connection that prevents leakage current accumulation through the substrate while allowing the doped regions to be positioned closer together, thereby enabling device size reduction without compromising reliability
2Volume of moving object
If spaces between internal elements are reduced to shrink device size, then more internal available spaces are released, but gate induced drain leakage occurs due to band-to-band tunneling
Solution Approach 1:
The conductive contact serves as a mediator that enables reduced spacing between doped regions while preventing the harmful GIDL effect. By providing a direct electrical connection through the substrate, it eliminates the need for large spacing that would otherwise be required to prevent band-to-band tunneling, thus releasing internal available spaces without generating leakage current
Solution Approach 2:
The conductive contact creates an equipotential connection between the first conductive type doped region and the second conductive type doped region through the substrate. This equalizes the electrical potential across the substrate region, preventing the voltage differential that would drive band-to-band tunneling and GIDL, thereby allowing closer spacing without harmful leakage effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces parasitic substrate resistance and improves current conduction efficiency by minimizing latch-up effects and internal space utilization, allowing for further size reduction without additional spacing requirements.
Implementation Method 1
external sources with different bias voltages (for example, one side is connected to a power cable and the other is grounded) may cause gate induced drain leakage (GIDL) due to band-to-band tunneling (BTBT)
Implementation Method 2
filling a contact material in the recess to form a conductive contact
Data Source
AI summary
A semiconductor device is provided in some embodiments of the present disclosure, including: a substrate, a plurality of first conductive type doped regions, a plurality of second conductive type doped regions and a conductive contact. The plurality of first conductive type doped regions are disposed in the substrate. The plurality of second conductive type doped regions are disposed in the substrate. The conductive contact is disposed in the substrate, in which the first conductive type doped regions are between the conductive contact and the plurality of second conductive type doped regions. A method of manufacturing a semiconductor device is further provided in some embodiments of the present disclosure.