Semiconductor Contact Plug Flatness via Capping Pattern Planarization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing integration of semiconductor devices leads to varying contact plug densities across different regions, resulting in uneven flatness due to the planarizing process, causing height differences between regions in semiconductor devices.
Innovation Solution
A method for fabricating semiconductor devices that involves forming gate electrodes with varying levels of integration, patterning interlayer dielectrics to create specific contact holes, filling conductive layers, and performing a planarizing process to expose capping patterns and form contact plugs, ensuring uniformity and electrical isolation across regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If contact plugs are formed with varying density across different regions to meet integration requirements, then device functionality is improved, but height differences and uneven flatness are generated between regions
Solution Approach 1:
The patent applies local quality by forming different types of contact holes in different regions: first contact holes in the memory cell region that expose the semiconductor substrate, and second contact holes in the peripheral circuit region that expose only the capping pattern and maintain a distance from the gate conductive pattern. This regional differentiation allows each region to have optimized contact plug density while the unified planarizing process maintains overall flatness across the substrate.
2Manufacturing precision
If a planarizing process is performed to improve flatness, then height differences between regions are reduced, but the complexity of the manufacturing process increases
Solution Approach 1:
The patent applies preliminary action by forming the gate electrodes with capping patterns before forming the contact holes. The capping patterns are prepared in advance to define the regions where second contact holes will be formed, allowing the planarizing process to be performed uniformly across the entire substrate without requiring separate processing steps for different regions.
3Reliability
If contact holes are formed to expose the semiconductor substrate in the memory cell region, then electrical connection is improved, but the risk of short circuits increases if contact holes are not properly isolated
Solution Approach 1:
The patent applies the intermediary principle by using the gate electrode structure with capping patterns as a mediator between the semiconductor substrate and the contact plugs. The gate electrode acts as an intermediate layer that provides electrical connection pathways while the capping pattern serves as an isolating barrier that prevents direct contact between adjacent contact holes, thereby eliminating short circuit risks.
Data Source
AI summary
A method for fabricating a semiconductor device includes providing a semiconductor substrate including a memory cell region and peripheral circuit regions. Gate electrodes including gate conductive patterns and capping patterns are formed on the memory cell region and the peripheral circuit regions. An interlayer dielectric covering the gate electrodes is formed. The interlayer dielectric is patterned to form first contact holes exposing the semiconductor substrate along side of the gate electrode in the memory cell region and second contact holes exposing a portion of the capping pattern in the peripheral circuit region such that a bottom surface of the second contact hole is spaced apart from a top surface of the gate conductive pattern. A first plug conductive layer is filled in the first contact holes and a second plug conductive layer is filled in the second contact holes. A planarizing process is performed to expose the capping patterns such that first contact plugs are formed in the memory cell region and second contact plugs are formed in the peripheral circuit region.