Semiconductor Contact Plug Grain Size Control
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Solution Overview
Problem
The existing two-step process for forming conductive layers in DRAMs, involving chemical vapor deposition (CVD) and physical vapor deposition (PVD), results in severe surface roughness and mismatched grain sizes, leading to high resistance and pattern toppling issues during lithography and etching processes.
Innovation Solution
A semiconductor structure and manufacturing method featuring a conductive layer with consistent grain size, formed by one-step CVD, and a barrier layer over mesas and blocks, followed by chemical mechanical planarization to expose a smooth contact surface, ensuring compatibility with subsequent lithography and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a two-step process (CVD followed by PVD) is used to form the conductive layer, then the surface roughness is reduced to enable photolithography patterning, but the process complexity and cost increase
Solution Approach 1:
The patent combines the CVD and PVD processes into a single integrated process where a conductive layer is deposited using CVD, then in-situ plasma treatment is applied to reduce surface roughness. This merging eliminates the need for separate PVD deposition and intermediate processing steps, reducing overall process complexity while maintaining surface quality suitable for photolithography patterning
2Manufacturing precision
If a two-step process (CVD followed by PVD) is used to form the conductive layer, then the surface roughness is reduced, but the grain size mismatch causes necking connection and high resistance
Solution Approach 1:
The patent controls the grain size of the CVD-deposited conductive layer by adjusting deposition parameters such as temperature, pressure, and precursor flow rates. Additionally, the in-situ plasma treatment parameters (power, gas flow, duration) are optimized to reduce surface roughness without significantly altering grain structure. This ensures grain size consistency between the conductive layer and subsequent layers, preventing necking connections and maintaining low electrical resistance
3Manufacturing precision
If a two-step process (CVD followed by PVD) is used to form the conductive layer, then the surface is suitable for patterning, but pattern toppling occurs in subsequent processes
Solution Approach 1:
The patent applies in-situ plasma treatment immediately after CVD deposition to pre-condition the conductive layer surface. This preliminary action reduces surface roughness and creates a more uniform surface morphology before photolithography patterning, preventing pattern toppling during subsequent processing steps by ensuring adequate mechanical support and adhesion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method produces a smooth and flat contact surface for the conductive layer, reducing necking connections and high resistance, thereby improving the reliability of DRAM manufacturing processes.
Implementation Method 1
Currently, the contact plug of the DRAM is formed by chemical vapor deposition (CVD) followed by physical vapor deposition (PVD)
Implementation Method 2
Currently, the contact plug of the DRAM is formed by chemical vapor deposition (CVD) followed by physical vapor deposition (PVD)
Implementation Method 3
followed by chemical mechanical planarization to expose a smooth contact surface
Data Source
AI summary
The present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a semiconductor substrate, a dielectric layer, a barrier layer, and a conductive layer. The semiconductor substrate has a plurality of mesas. The dielectric layer is disposed over the semiconductor substrate and has a plurality of blocks disposed over the mesas, respectively. The barrier layer is formed over a first lateral surface of the mesa, a second lateral surface of the block, an upper surface of the semiconductor substrate adjacent to the first lateral surface, and a front surface of the dielectric layer adjacent to the second lateral surface. The conductive layer has a base and a plurality of protrusions extending from the base and in contact with the barrier layer disposed over the upper surface, the first lateral surface, and the second lateral surface. A grain size of the base and the protrusions is consistent.