Semiconductor Contact Trench for Low On-State Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in achieving low on-state voltage and high robustness against avalanche and over-current turn-off, particularly due to suboptimal electrical contacts to semiconductor regions in insulated gate field effect transistors (IGFETs) and insulated gate bipolar transistors (IGBTs.
Innovation Solution
A method for manufacturing semiconductor devices involving the formation of first and second contact layers, where a contact trench is created to directly connect to the semiconductor body, allowing for improved electrical contact through a self-aligned process, with the first contact layer lining the trench and the second contact layer forming a direct electrical connection at the bottom side, enabling efficient contact to both n- and p-conductivity type regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact methods are used, then manufacturing process is simpler, but electrical connection quality deteriorates
Solution Approach 1:
The contact structure is segmented into multiple functional layers: a first contact layer (metal) for electrical connection, a second contact layer (semiconductor) for region selection, and a third contact layer (dielectric) for isolation. This segmentation allows each layer to perform its specific function optimally, improving overall electrical connection quality while maintaining manufacturing feasibility through sequential deposition processes.
2Manufacturing precision
If multiple photolithography processes are used, then contact precision is improved, but manufacturing complexity increases
Solution Approach 1:
The first contact layer is formed by conformal deposition over the entire first surface before the contact trench is etched. This preliminary formation of the contact layer simplifies subsequent processing steps, as the layer is already in place to be patterned and connected, reducing the need for additional alignment-critical photolithography steps while maintaining precision.
Solution Approach 2:
The conformal deposition process automatically forms the first contact layer with uniform thickness and proper coverage across the surface. The self-aligned nature of conformal deposition ensures that the contact layer precisely follows the underlying topography and feature boundaries without requiring separate alignment steps, thereby improving manufacturing precision while maintaining productivity.
3Reliability
If contact layer is removed completely, then contact resistance is reduced, but structural integrity deteriorates
Solution Approach 1:
The first contact layer is selectively removed only from the bottom side of the contact trench to expose the second semiconductor region for direct electrical contact. The contact layer is retained at the sidewalls and other areas where it provides structural support and electrical connection. This localized removal optimizes electrical contact performance at the critical interface while preserving the structural integrity and stability of the overall contact structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical connection to semiconductor regions, reducing contact resistance and improving the performance of IGFETs and IGBTs by allowing for a single photolithography process to form a trench contact structure, thereby addressing the limitations of existing contact methods.
Implementation Method 1
The first contact layer may be formed by a conformal deposition technique, for example by sputtering, by chemical vapor deposition (CVD) or by physical layer deposition (PLD).
Implementation Method 2
The dopants may be introduced by diffusion and/or ion implantation, for example. The highly doped contact layer may allow for an improved ohmic contact to the first semiconductor region.
Implementation Method 3
The dopants may be introduced by diffusion and/or ion implantation, for example.
Data Source
AI summary
An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench.