Semiconductor Control Circuit Annealing Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device manufacturing is to reduce manufacturing costs while maintaining the integrity of control circuits during high temperature annealing processes, which is essential for forming memory cells under the memory array without degrading the control circuit's characteristics.
Innovation Solution
A semiconductor device manufacturing method involves forming a control circuit on the surface of a substrate between the substrate and the memory array, using a multilayer interconnection with high melting point metals like Ti and W, and implanting carbon ions to suppress impurity diffusion and maintain low resistance contacts, allowing the control circuit to withstand high temperature annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high temperature annealing is performed to form memory cells collectively, then manufacturing efficiency and cost reduction are improved, but the control circuit characteristics are degraded due to thermal damage
Solution Approach 1:
The patent divides the semiconductor device into distinct functional regions: a first region containing the control circuit and a second region containing the memory cell array. This spatial segmentation allows the memory region to undergo high temperature annealing while the control circuit region is protected from thermal damage, resolving the contradiction between manufacturing efficiency and circuit reliability
Solution Approach 2:
The patent introduces an insulating layer as an intermediary structure between the control circuit and memory array. This insulating layer acts as a thermal barrier that protects the control circuit from the high temperature annealing process required for memory cell formation, enabling both high productivity and maintained circuit characteristics
2Area of stationary object
If the control circuit is placed directly under the memory array to reduce chip size, then device miniaturization is achieved, but the control circuit cannot withstand the high temperature annealing required for memory formation
Solution Approach 1:
The patent segments the device into a first region with the control circuit and a second region with the memory array, positioned adjacent to each other rather than directly overlapping. This segmentation maintains compact chip area while physically separating the heat-sensitive control circuit from the high-temperature processing zone
Solution Approach 2:
An insulating layer is introduced as a mediator between the control circuit and memory array regions. This intermediary structure provides thermal isolation, allowing the control circuit to be positioned close to the memory array for miniaturization while protecting it from annealing temperatures
3Ease of manufacture
If conventional interconnection structures are used in the control circuit, then manufacturing simplicity is maintained, but the structures cannot survive high temperature annealing processes
Solution Approach 1:
The patent changes the material parameters of the interconnection structure in the control circuit region by forming it with a high melting point material. This parameter change enables the interconnection to withstand high temperature annealing processes while maintaining manufacturing simplicity through standardized formation processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor devices with reduced chip size and increased operation speed by maintaining the control circuit's performance during the annealing process, thereby reducing manufacturing costs and enhancing memory array characteristics.
Implementation Method 1
implanting carbon, in the form of carbon ions, into the p-type semiconductor region
Implementation Method 2
the high temperature annealing within the manufacturing process
Data Source
AI summary
According to an embodiment, a method of manufacturing a semiconductor device including a memory array provided on a substrate, and a control circuit provided on a surface of the substrate between the substrate and the memory array, includes steps of forming, in an insulating layer covering a p-type semiconductor region and an n-type semiconductor region of the control circuit, a first contact hole communicating with the p-type semiconductor region; forming a contact plug, in contact with the p-type semiconductor region, within the first contact hole; forming, in the insulating layer, a second contact hole communicating with the n-type semiconductor region; and forming an interconnection contacting the contact plug and the n-type semiconductor region exposed within the second contact hole.