Semiconductor Package With Coplanar Redistribution Layers

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Solution Overview

Problem

Current semiconductor packaging technologies, such as fan-in packages, face challenges in accommodating semiconductor chips with a large number of I/O terminals or small sizes due to spatial limitations and the need for redistribution of connection pads, making it difficult to directly mount these packages on electronic device mainboards without using interposer substrates.

Innovation Solution

A semiconductor package design featuring a frame with a cavity and a wiring structure connecting opposing surfaces, a first redistribution layer connected to the wiring structure, a semiconductor chip with connection pads, and a second redistribution layer connected through vias, with an encapsulant covering the frame and having a planarized surface, allowing for stable formation of a fine backside redistribution layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If a fan-in semiconductor package is used, then the semiconductor chip can be packaged with connection pads, but the package size becomes large and cannot be directly mounted on mainboards without interposer substrates

Engineering Contradiction:

Improvepackage sizeVSAvoidmounting capability

Core Design Contradiction:

Volume of moving objectVSAdaptability or versatility

Solution Approach 1:

The patent transitions from a traditional fan-in package configuration to a fan-out package configuration by redistributing connection pads to regions outside the semiconductor chip footprint. This dimensional reorganization allows the package to maintain a compact size while expanding the functional area for mounting connections, enabling direct mounting on mainboards without requiring interposer substrates.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The package structure is segmented into distinct functional regions: the semiconductor chip area, the encapsulant region, and the fan-out region for redistribution layers. This segmentation allows independent optimization of each region, enabling the connection pads to be redistributed to areas outside the chip boundaries while maintaining compact overall package dimensions.

Inventive Principle:

Principle #1Segmentation

2Productivity

If connection pads are redistributed outside the semiconductor chip region, then more pins can be implemented in a compact size, but the backside redistribution layer formation becomes unstable

Engineering Contradiction:

Improvepin densityVSAvoidredistribution layer formation stability

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies for-backside-via formation before the encapsulant molding process. By pre-forming the via holes and conducting stability treatment on the backside surface, the structure is prepared in advance to withstand subsequent molding stresses. This preliminary action ensures that the backside redistribution layer maintains its dimensional stability and pattern fidelity during the encapsulant formation process, enabling stable manufacturing of fine-pitch redistribution structures.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements stability treatment on the backside surface of the substrate before forming the encapsulant. This treatment acts as a cushioning measure that prevents deformation and maintains the structural integrity of the backside redistribution layer during the molding process, ensuring manufacturing precision is maintained despite the complex redistribution geometry.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If the encapsulant surface is not coplanar with the wiring structure, then the chip is encapsulated, but the subsequent insulating layer formation becomes difficult

Engineering Contradiction:

Improvechip encapsulationVSAvoidinsulating layer formation

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent designs the encapsulant to have a upper surface that is substantially coplanar with the upper surface of the wiring structure. This preliminary geometric configuration ensures that when the insulating layer is subsequently formed, it can be applied uniformly without requiring complex planarization processes, significantly easing manufacturing while maintaining reliable chip encapsulation.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11158581B2Semiconductor package having semiconductor chip between first and second redistribution layers

Publication Date: 2021.10.26 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package may include: a frame having a cavity and including a wiring structure connecting first and second surfaces of the frame to each other; a first connection structure d on the second surface of the frame and including a first redistribution layer connected to the wiring structure; a semiconductor chip on the first connection structure within the cavity and having connection pads connected to the first redistribution layer; an encapsulant encapsulating the semiconductor chip, covering the first surface of the frame, and having an upper surface substantially coplanar with an upper surface of the wiring structure; and a second connection structure including an insulating layer disposed on the upper surfaces of the encapsulant and the wiring structure, a second redistribution layer on the insulating layer, and vias penetrating through the insulating layer and connecting the wiring structure and the second redistribution layer.