Semiconductor Device Crack Guidance via Interlayer Insulating Steps
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Solution Overview
Problem
Existing semiconductor devices face challenges in preventing cracks generated during dicing from reaching circuit regions while maintaining reliability, as metal layers used for crack prevention can undergo oxidation, leading to reduced reliability.
Innovation Solution
A semiconductor device configuration featuring a semiconductor substrate with a circuit region and a chip outer peripheral region, including a first and second interlayer-insulating film with specific steps and a seal ring, where the surface of the chip outer peripheral region side is lower than the circuit region side, guiding cracks away from the circuit region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the scribe line width is increased to accommodate crack progression, then cracks are contained within the scribe line, but the chip size increases
Solution Approach 1:
The crack guidance function is transitioned from a two-dimensional planar structure (wide scribe line) to a three-dimensional vertical structure (step configuration with interlayer-insulating films). The steps create vertical surfaces that guide cracks upward in the Z-dimension, allowing the use of narrower scribe lines while maintaining crack containment effectiveness
Solution Approach 2:
The crack prevention structure is segmented into multiple functional layers: the semiconductor substrate, first interlayer-insulating film with first step, and second interlayer-insulating film with second step. This segmentation allows each layer to contribute specifically to crack guidance and containment, improving efficiency and reducing the required scribe line width
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively prevents cracks from reaching the circuit region, maintaining reliability by concentrating stress on the steps and guiding the crack upward, thereby avoiding exposure of metal layers that could cause oxidation.
Implementation Method 1
concentrating stress on the steps and guiding the crack upward
Data Source
Figure 1A~1B
Figure 2
Figure 3A~3B
AI summary
A semiconductor device includes a semiconductor substrate 101 containing a circuit region CR and a chip outer peripheral region PR provided adjacent thereto, a first interlayer-insulating film 102 provided on the semiconductor substrate 101, a second interlayer-insulating film 104 provided on the first interlayer-insulating film 102, a first step ST1 provided between the semiconductor substrate 101 and the first interlayer-insulating film 102 so that the chip outer peripheral region PR side is lower than the circuit region CR side in the chip outer peripheral region PR, and a second step ST2 located on the circuit region CR side relative to the first step ST1 and provided in the second interlayer-insulating film 104 in the chip outer peripheral region PR.