Semiconductor Data Transfer Unit with Reduced Voltage Swing
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Solution Overview
Problem
Conventional semiconductor devices experience increased data access time and degradation in high-frequency operation characteristics due to large data swing width on global data bus lines, leading to data errors during transfer.
Innovation Solution
A semiconductor device with a data transfer unit that adjusts the driving period of data on the global data bus line by using delay signals and transfer control signals to limit the data swing between external voltage and ground voltage, preventing full swing and reducing data errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is fully swung between external voltage VDD and ground voltage VSS on the global data bus line, then data transfer reliability is improved, but data access time increases and high-frequency operation characteristics degrade
Solution Approach 1:
The patent changes the voltage parameter by introducing a reduced swing voltage level (VDD/2) instead of using the full external voltage VDD. The data transfer unit drives data to this intermediate voltage level, reducing the voltage swing width on the global data bus line while maintaining sufficient signal integrity for reliable data transfer.
2Reliability
If data is fully swung between external voltage VDD and ground voltage VSS on the global data bus line, then data transfer reliability is improved, but high-frequency operation characteristics degrade
Solution Approach 1:
The patent changes the voltage parameter by introducing a reduced swing voltage level (VDD/2) instead of using the full external voltage VDD. The data transfer unit drives data to this intermediate voltage level, reducing the voltage swing width on the global data bus line while maintaining sufficient signal integrity for reliable data transfer.
3Loss of time
If data is not fully swung between external voltage VDD and ground voltage VSS, then data access time is reduced, but data sensing accuracy deteriorates causing data errors
Solution Approach 1:
The patent changes the voltage parameter by introducing a reduced swing voltage level (VDD/2) instead of using the full external voltage VDD. The data transfer unit drives data to this intermediate voltage level, reducing the voltage swing width on the global data bus line while maintaining sufficient signal integrity for reliable data transfer.
Solution Approach 2:
The delay controller uses feedback from delay signals (delayed versions of the data signal) to dynamically adjust the driving period of the data transfer unit. This feedback mechanism ensures that data is driven for the optimal duration to reach the reduced swing level without over-driving, thereby maintaining data sensing accuracy while minimizing access time.
4Productivity
If data swing width is reduced on the global data bus line, then data transfer rate increases, but data transfer reliability may deteriorate
Solution Approach 1:
The patent changes the voltage parameter by introducing a reduced swing voltage level (VDD/2) instead of using the full external voltage VDD. The data transfer unit drives data to this intermediate voltage level, reducing the voltage swing width on the global data bus line while maintaining sufficient signal integrity for reliable data transfer.
Solution Approach 2:
The delay controller uses feedback from delay signals (delayed versions of the data signal) to dynamically adjust the driving period of the data transfer unit. This feedback mechanism ensures that data is driven for the optimal duration to reach the reduced swing level without over-driving, thereby maintaining data sensing accuracy while minimizing access time.
Data Source
AI summary
A semiconductor device is disclosed which increases the data transfer rate in transferring data output from an input/output sense amplifier via a global data bus line by reducing the swing width of the data placed on the global data bus line. The semiconductor device may include a data transfer unit which receives first data, and outputs second data obtained by driving the first data to a predetermined level to a data transfer line; a data receiver which receives the second data transferred via the data transfer line; a delay which outputs a plurality of delay signals respectively obtained by delaying the second data outputted from the data transfer unit by different delay periods; a delay controller which selects one of the delay signals in accordance with an operation mode of the semiconductor device, and outputs at least one adjustment signal for adjusting a driving period of the data transfer unit for the first data based on the delay period of the selected delay signal; and a transfer controller which receives the first data and the at least one adjustment signal, and outputs at least one transfer control signal for controlling the operation of the data transfer unit, based on the received first data and adjustment signal.