Semiconductor Device De-wetting Structures for Delamination Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in further reducing the physical size of semiconductor devices while maintaining functionality, as traditional bonding processes are inefficient and prone to delamination, especially with the increasing demand for miniaturization, higher speed, and lower power consumption.
Innovation Solution
A method involving the use of a carrier substrate with an adhesive layer, polymer layer, seed layers, and vias to facilitate the stacking and bonding of semiconductor devices, where the polymer layer is patterned to expose seed layers, reducing delamination risks and enabling efficient electrical connections through redistribution layers and external connectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional bonding processes are used to stack semiconductor devices, then device integration is achieved, but delamination occurs and bonding reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by forming an adhesive layer on the carrier substrate before depositing the seed layer and via structure. This pre-prepared adhesive interface ensures proper bonding when the semiconductor die is stacked, preventing delamination issues that occur with traditional bonding processes where adhesion is not established in advance.
Solution Approach 2:
The patent introduces an adhesive layer as an intermediary substance between the carrier substrate and the semiconductor die stack. This intermediary layer mediates the bonding interface, providing reliable adhesion and preventing direct contact between incompatible surfaces that would cause delamination in traditional bonding processes.
2Productivity
If minimum feature size is reduced to increase integration density, then more components fit in given area, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs parameter changes by systematically reducing the dimensions of vias, seed layers, and adhesive features to sub-20 nm scales while maintaining manufacturing control. The via openings are reduced to 50-200 nm, seed layer thickness to 10-50 nm, and adhesive layer to 5-20 nm, achieving high integration density while managing precision requirements through controlled parameter scaling.
Solution Approach 2:
The patent applies segmentation by dividing the bonding interface into distinct functional layers (adhesive layer, seed layer, via structure) with clearly defined dimensions and properties. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall manufacturing precision even at reduced feature sizes.
3Reliability
If sophisticated bonding techniques are used to stack devices, then device functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple functions into the via structure, which simultaneously serves as the bonding interface, electrical connection pathway, and mechanical alignment feature. This consolidation reduces manufacturing complexity compared to separate processes for bonding, electrical connection, and alignment, while maintaining sophisticated device functionality.
Solution Approach 2:
The via structure is designed with multi-functionality, serving as both the bonding interface for stacking and the electrical interconnection pathway. The seed layer within the via provides both structural support and electrical conductivity, reducing the need for separate specialized components and simplifying the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of smaller, more efficient semiconductor devices with improved bonding and reduced delamination risks, enhancing manufacturing yield and device performance.
Implementation Method 1
a carrier substrate with an adhesive layer
Implementation Method 2
the polymer layer is patterned to expose seed layers
Implementation Method 3
enabling efficient electrical connections through redistribution layers and external connectors
Data Source
AI summary
An integrated fan out package on package architecture is utilized along with de-wetting structures in order to reduce or eliminated delamination from through vias. In embodiments the de-wetting structures are titanium rings formed by applying a first seed layer and a second seed layer in order to help manufacture the vias. The first seed layer is then patterned into a ring structure which also exposes at least a portion of the first seed layer.