Semiconductor Device Thermal Expansion Balance
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Solution Overview
Problem
Semiconductor devices with BGA structures face issues of stress and bending due to thermal expansion mismatches between the semiconductor chip and the wiring substrate, leading to potential disconnection of external electrodes, especially when stacked, which reduces the reliability of secondary mounting.
Innovation Solution
A semiconductor device design featuring an insulating substrate with an opening, where a semiconductor chip is disposed within the opening, and a sealing resin layer is used to balance thermal expansion by adjusting the thickness and coefficient of thermal expansion of the insulating and sealing layers, reducing stress and bending.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a semiconductor chip is bonded and fixed to the wiring substrate through adhesive, then the chip is securely mounted, but stress is generated due to thermal expansion mismatch which may break external electrodes
Solution Approach 1:
The patent applies parameter changes by carefully selecting and adjusting the thickness and coefficient of thermal expansion of the insulating layer and sealing layer. The insulating layer thickness is set to 10-100 μm and the sealing layer thickness to 100-500 μm, with their CTE values chosen to balance the thermal expansion between the chip and substrate, thereby reducing stress on external electrodes while maintaining secure mounting
Solution Approach 2:
The patent uses composite material structure by combining multiple layers with different properties: the insulating substrate, insulating layer, sealing layer, and adhesive layer form a composite structure where each layer is selected for its specific thermal expansion characteristics. This composite approach allows balancing thermal expansion across the entire assembly to prevent electrode breakage
2Length of moving object
If a support tape is used to dispose the semiconductor chip in the opening, then the device thickness is reduced, but poor thermal expansion balance causes stress or bending leading to disconnection
Solution Approach 1:
The patent replaces the support tape with an insulating layer having controlled thickness (10-100 μm) and specific thermal expansion properties. This parameter change eliminates the thermal expansion mismatch problem inherent in support tape while maintaining the thin-profile advantage, preventing stress and bending that would cause disconnection
Solution Approach 2:
The insulating layer acts as an intermediary between the chip and the external environment, providing both mechanical support and thermal expansion buffering. Unlike support tape, this insulating layer is integrated into the substrate structure and has matched CTE properties, serving as a mediator that prevents stress transmission while enabling the reduced thickness design
3Ease of manufacture
If the insulating layer and sealing layer thicknesses are not optimized, then manufacturing is simpler, but thermal expansion imbalance causes stress and bending affecting secondary mounting
Solution Approach 1:
The patent establishes specific parameter ranges for the insulating layer (10-100 μm) and sealing layer (100-500 μm) thicknesses, along with their coefficient of thermal expansion values. These parameter specifications balance manufacturing simplicity with thermal expansion control, ensuring that stress and bending are minimized while maintaining ease of fabrication within the defined ranges
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of secondary mounting by minimizing stress and bending, preventing external electrode disconnection and improving the thermal expansion balance within the semiconductor device.
Implementation Method 1
the balance of thermal expansion is poor between the support tape disposed on one surface of the wiring substrate and the sealing member disposed on the other surface thereof
Data Source
AI summary
A semiconductor device includes an insulating substrate, a semiconductor chip, an insulating layer, and a sealing layer. The insulating substrate has an opening. A semiconductor chip is disposed in the opening. An insulating layer is disposed on a first surface of the insulating substrate. The insulating layer covers the opening. The sealing layer is disposed on a second surface of the insulating substrate. The sealing layer seals the semiconductor chip and the opening.