Semiconductor Device Termination Region for Reflux Current Handling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices like MOSFETs, the operation of built-in p-n diodes leads to crystal defects due to recombination energy, increasing ON resistance and conduction loss, which complicates long-term stability and increases chip size and cost.
Innovation Solution
A semiconductor device configuration with a drift layer, well regions, separation regions, Schottky electrodes, and ohmic electrodes is implemented, where the second Schottky electrode is placed outside the active region to suppress voltage and prevent p-n diode operation, allowing for increased reflux current without increasing chip size or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-n diode is operated in forward direction, then minority carriers are implanted in drift layer, but recombination energy causes crystal defects that increase ON resistance and conduction loss
Solution Approach 1:
The patent extracts the harmful p-n diode operation from the active region by providing a dedicated termination region with a p-n junction structure separate from the main active area. This allows reflux current to be handled without causing crystal defects in the active region, thereby maintaining low conduction loss and long-term stability.
Solution Approach 2:
The termination region acts as an intermediary structure that handles the harmful effects of p-n diode operation. By placing the p-n junction in the termination region rather than the active region, the patent mediates between the need for reflux current handling and the need to prevent crystal defects in the active area.
2Productivity
If reflux current is increased to reduce chip size, then more current flows through MOSFET, but p-n diode operates faster in unit cells close to termination, increasing ON resistance
Solution Approach 1:
The patent applies local quality by creating a termination region with different structural characteristics from the active region. The termination region has a specific p-n junction configuration that is optimized for handling reflux current without causing the same crystal defect issues in the active region, allowing high reflux current capacity without increased ON resistance.
Solution Approach 2:
The patent segments the device structure into distinct active region and termination region. This segmentation allows the termination region to handle high reflux currents through its dedicated p-n junction structure, while the active region maintains its low resistance characteristics without being affected by p-n diode operation.
3Reliability
If chip size is increased to limit reflux current, then p-n diode operation is suppressed, but chip cost increases
Solution Approach 1:
The patent changes the structural parameters by introducing a termination region with a specific p-n junction configuration. This parameter change allows the device to handle reflux current effectively without requiring increased chip size, as the termination region's structure suppresses harmful p-n diode operation in the active region while maintaining compact dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses p-n diode operation, enhancing reflux current flow and reducing chip size and cost by minimizing ON resistance and conduction loss, thereby improving the semiconductor device's stability and efficiency.
Implementation Method 1
Patent Document 1 proposes a method of using Schottky barrier diodes (SBDs) as reflux diodes that are built in unit cells of MOSFETs
Implementation Method 2
A p-n diode is built in a semiconductor device such as a MOSFET. Thus, when the p-n diode operates in a state in which voltage is applied to the p-n diode in a forward direction
Implementation Method 3
a first ohmic electrode provided over each of the first well regions while sandwiching the first Schottky electrode therein in plan view
Data Source
AI summary
A device that increases a value of current flowing through a whole chip until a p-n diode in a unit cell close to a termination operates and reduces a size of the chip and a cost of the chip resulting from the reduced size. The device includes a second well region located to sandwich the entirety of a plurality of first well regions therein in plan view, a third separation region located to penetrate the second well region from a surface layer of the second well region in a depth direction, and a second Schottky electrode provided on the third separation region.