Semiconductor Device With Annular Deep Trench Isolation
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Solution Overview
Problem
The existing semiconductor devices with a trench gate structure, such as VDMOSFETs, face challenges in integrating multiple devices on the same substrate due to voltage isolation issues and lithographic process defects caused by step formation during epitaxial growth, which complicates mixed mounting and resist pattern exposure.
Innovation Solution
A semiconductor device design featuring an annular deep trench that reaches an insulating layer, allowing for a vertical current path without substrate conduction, thereby eliminating step formation and enabling mixed mounting of VFETs with other devices by electrically isolating the transistor region from the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the drain electrode is arranged on the rear surface of the N+-type substrate, then the device area is reduced, but it is difficult to isolate the VDMOSFET region from the remaining substrate region, preventing mixed mounting with other devices
Solution Approach 1:
The substrate is segmented into isolated regions using deep trenches filled with insulating material. These trenches divide the N+-type substrate into separate functional areas, allowing VDMOSFETs to be isolated from other devices while maintaining the vertical current path advantage. The segmentation creates electrically independent zones without requiring separate substrates.
Solution Approach 2:
An insulating layer and deep trench structure serve as intermediary elements between the drain electrode on the rear surface and other potential devices. This intermediary isolation structure enables voltage separation and prevents electrical interference, allowing mixed mounting of different device types on the same substrate while maintaining the compact vertical design.
2Reliability
If a box layer is removed from the transistor forming region to ensure current path conduction, then current flow is improved, but a step is formed on the surface during epitaxial growth, causing lithographic process defects
Solution Approach 1:
The deep trench isolation structure is formed preliminarily before epitaxial growth, creating a predefined isolation pattern that guides subsequent processing. The trench structure is prepared in advance with proper depth and positioning, ensuring that the epitaxial layer grows uniformly without forming harmful steps at the trench edges, thus preventing lithographic defects.
Solution Approach 2:
The isolation structure extends into the vertical dimension with deep trenches reaching through the substrate thickness. This three-dimensional isolation approach separates the current path conduction requirement from the surface topology, allowing good electrical contact in the vertical dimension while maintaining a flat surface in the horizontal dimension for lithographic processing.
3Strength
If the box layer thickness is increased to increase withstand voltage, then voltage handling capability is improved, but the step size on the surface increases, worsening lithographic exposure quality
Solution Approach 1:
The voltage withstand capability is enhanced in the vertical dimension by increasing the depth of the deep trench isolation structure and the thickness of the epitaxial layer, rather than increasing the horizontal footprint. This allows high voltage handling while maintaining a flat surface topology suitable for lithographic processing, as the critical dimensions are controlled in the vertical dimension.
Solution Approach 2:
The box layer or insulating material is strategically positioned and sized to provide sufficient electrical isolation and voltage withstand capability only where needed for device operation. The local thickness and positioning are optimized to achieve the required breakdown voltage while minimizing surface step formation, allowing adequate isolation without excessive step height that would harm lithography.
Data Source
AI summary
The semiconductor device according to the present invention includes a semiconductor substrate, an insulating layer laminated on the semiconductor substrate, a semiconductor layer laminated on the insulating layer, an annular deep trench having a depth reaching the insulating layer from the surface of the semiconductor layer, a source region formed on the surface layer of the semiconductor layer in a transistor forming region enclosed with the deep trench, a drain region formed on the surface layer of the semiconductor layer in the transistor forming region, an isolation region formed between the source region and the drain region for electrically isolating the source region and the drain region from each other, and a current path formed on the transistor forming region for guiding a current from the drain region to a position opposite to the source region in the vertical direction perpendicular to the surface of the semiconductor device.