3D Semiconductor Device Vertical Integration Architecture
Solution Overview
Problem
The existing two-dimensional semiconductor devices face limitations in increasing their degree of integration due to the high costs and complexities associated with refining patterns, which restricts their price and performance.
Innovation Solution
A semiconductor device with a three-dimensional architecture is proposed, featuring a semiconductor pattern on a substrate with vertically stacked cell gate conductive patterns, cell vertical structures, and bit line contact plugs, along with peripheral interconnection structures that enhance integration by vertically connecting the memory cell array to the peripheral circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use refined patterns to increase integration, then integration density improves, but manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking architecture. Multiple memory cell layers are stacked vertically with intermediate substrates, allowing integration density to increase in the vertical dimension rather than requiring continuous refinement of two-dimensional patterns. This dimensional change fundamentally resolves the contradiction by achieving higher integration without proportionally increasing pattern refinement complexity.
2Quantity of substance
If two-dimensional semiconductor devices continue scaling, then integration increases, but manufacturing cost increases due to super-high price refinement systems
Solution Approach 1:
The three-dimensional memory structure is divided into multiple discrete memory cell layers separated by intermediate substrates. Each layer can be manufactured and processed independently to some extent, then stacked together. This segmentation allows for more manageable manufacturing processes compared to continuous two-dimensional scaling, reducing the need for increasingly expensive refinement systems while achieving higher integration through vertical stacking.
3Area of stationary object
If peripheral circuits are integrated in two-dimensional layout, then device area is utilized, but interconnection complexity and manufacturing difficulty increase
Solution Approach 1:
Peripheral circuits are integrated into the intermediate substrates between memory cell layers rather than being laid out in the same two-dimensional plane as memory cells. This vertical integration in the third dimension reduces interconnection complexity by shortening connection paths and eliminating the need for complex lateral routing that would be required in a purely two-dimensional layout.
Data Source
AI summary
Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor pattern.