Power Semiconductor Die Thermal Dissipation Area
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Solution Overview
Problem
Wide bandgap power semiconductor dies face challenges with heat dissipation and manufacturing yield due to high power density, often requiring operation at lower voltages and currents than rated, limiting their thermal performance.
Innovation Solution
Incorporating a thermal dissipation area surrounding the edge termination area of the power semiconductor die, which reduces thermal resistance without increasing the active area, thereby allowing higher operating voltages and currents while improving manufacturing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the active area is increased to reduce on-state resistance and improve thermal dissipation, then thermal performance improves, but manufacturing yield decreases
Solution Approach 1:
The drift layer is segmented into three distinct functional areas: active area for current conduction, edge termination area for electric field management, and thermal dissipation area for heat management. This segmentation allows each area to be optimized independently, enabling improved thermal performance through the dedicated thermal dissipation area without increasing the active area, thereby maintaining manufacturing yield.
Solution Approach 2:
Different regions of the drift layer are assigned different qualities and functions: the active area has high doping concentration for low on-state resistance, the edge termination area has specific implantation patterns for electric field reduction, and the thermal dissipation area is optimized purely for thermal conductivity. This local differentiation enables thermal improvement without compromising yield by keeping the active area size constant.
2Power
If the active area is increased to handle higher power density, then power handling capability improves, but manufacturing yield decreases
Solution Approach 1:
The drift layer is divided into active area, edge termination area, and thermal dissipation area, allowing power handling capability to be enhanced through the thermal dissipation area rather than increasing active area. This segmentation enables higher power density management while maintaining the active area size within optimal yield ranges.
Solution Approach 2:
Instead of increasing power handling capability by expanding the active area in two dimensions, the invention adds a third functional dimension by incorporating a dedicated thermal dissipation area. This dimensional approach allows higher power handling through improved thermal management without the penalty of reduced manufacturing yield associated with larger active areas.
3Temperature
If operating voltage and current are reduced due to thermal limitations, then thermal performance is maintained, but device utilization decreases
Solution Approach 1:
The thermal dissipation area is specifically optimized for thermal management with appropriate doping concentrations and structural characteristics, allowing the device to maintain rated operating voltages and currents without thermal runaway. This localized thermal optimization enables full device utilization while maintaining safe operating temperatures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The thermal dissipation area enhances thermal performance and yield by allowing increased operating voltages and currents without increasing on-state resistance, providing a better tradeoff between yield and performance compared to conventional designs.
Implementation Method 1
The thermal dissipation area is configured to reduce a thermal resistance of the power semiconductor die
Implementation Method 2
The active area includes one or more implanted regions, and is configured to conduct current during a conduction mode of operation
Implementation Method 3
The edge termination area includes one or more implanted termination regions, and is configured to reduce an electric field during a blocking mode of operation
Data Source
AI summary
A power semiconductor die includes a substrate and a drift layer on the substrate. The drift layer includes an active area, an edge termination area surrounding the active area, and a thermal dissipation area surrounding the edge termination area. The thermal dissipation area is configured to reduce a thermal resistance of the power semiconductor die. By providing the thermal dissipation area, the operating voltage and/or current of the power semiconductor die can be increased without an increase in the active area. Further, the manufacturing yield of the power semiconductor die can be improved.