Semiconductor Device with Dual-Modulus Resin for Stress Relief
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Solution Overview
Problem
Semiconductor devices with stacked semiconductor chips face connection defects due to high elastic modulus mold resins, leading to cracks and peeling in the bump and electrode layers, which are exacerbated by thermal stress and bending.
Innovation Solution
A semiconductor device design featuring a bonding portion with a low elastic modulus between semiconductor elements and a resin portion with a higher elastic modulus, which alleviates stress and maintains a stable connection by using materials like acrylic resin for bonding and epoxy resin for sealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a mold resin with high elastic modulus is used for sealing, then the resin portion has sufficient structural strength, but connection defects occur in the bump and electrode layers due to stress concentration
Solution Approach 1:
The patent applies local quality by using a bonding portion with low elastic modulus specifically at the interface between semiconductor elements where stress concentration occurs, while using a different resin portion with high elastic modulus for sealing. This localized differentiation of material properties resolves the contradiction by providing both stress relief at critical interfaces and structural strength for sealing.
Solution Approach 2:
The patent uses composite materials by combining a bonding portion made of low elastic modulus material (acrylic resin) with a resin portion made of high elastic modulus material (epoxy resin). This composite structure allows the device to simultaneously achieve stress relief and structural strength, resolving the technical contradiction between these two opposing requirements.
2Device complexity
If a single material is used for both bonding and sealing, then the structure is simple, but it cannot simultaneously provide stress relief and structural strength
Solution Approach 1:
The patent segments the sealing structure into two distinct portions: a bonding portion for stress relief and a resin portion for structural strength. This segmentation allows each portion to be optimized for its specific function, with the bonding portion using low elastic modulus material to prevent connection defects and the resin portion using high elastic modulus material for structural integrity.
Solution Approach 2:
The patent applies local quality by assigning different material properties to different regions of the sealing structure. The bonding portion at the critical interface uses low elastic modulus material for stress relief, while the outer resin portion uses high elastic modulus material for structural strength, optimizing each region for its specific functional requirement.
3Stability of the object's composition
If high elastic modulus resin is used, then packaging stability is improved, but thermal stress and bending are exacerbated causing connection defects
Solution Approach 1:
The patent applies parameter changes by varying the elastic modulus parameter across different portions of the sealing structure. The bonding portion uses low elastic modulus to reduce thermal stress and bending effects, while the resin portion uses high elastic modulus for packaging stability. This parameter differentiation resolves the contradiction between stability and stress resistance.
Solution Approach 2:
The patent uses composite materials with different elastic modulus characteristics to simultaneously achieve packaging stability and resistance to thermal stress. The combination of low elastic modulus bonding portion and high elastic modulus resin portion creates a composite structure that balances these opposing requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses connection defects in the bump and enhances resistance to external stress, ensuring a stable electrical connection while minimizing package bending and thermal expansion-induced stress.
Implementation Method 1
The bonding portion is between the first semiconductor element and the second semiconductor element, bonds the first semiconductor element to the second semiconductor element, and has a first elastic modulus.
Implementation Method 2
The resin portion has a second elastic modulus higher than the first elastic modulus. A first portion of the resin portion is between the first semiconductor element and the second semiconductor element.
Implementation Method 3
The bump is between the first semiconductor element and the second semiconductor element and electrically connects the first semiconductor element and the second semiconductor element.
Implementation Method 4
The resin portion has a second elastic modulus higher than the first elastic modulus. A third portion of the resin portion is overlapped with the first semiconductor element and the second semiconductor element in a second direction intersecting with a first direction going from the wiring substrate toward the first semiconductor element.
Data Source
AI summary
A semiconductor device includes a wiring substrate, a first semiconductor element, a second semiconductor element, a bump, a bonding portion, and a resin portion. The second semiconductor element is between the wiring substrate and the first semiconductor element. The bump is between the first and second semiconductor elements and electrically connects the first and second semiconductor elements. The bonding portion is between the first and second semiconductor elements, bonds the first semiconductor element to the second semiconductor element, and has a first elastic modulus. The resin portion has a second elastic modulus higher than the first elastic modulus. The resin portion is between the first and second semiconductor elements. The first semiconductor element is between a second portion of the resin portion and the wiring substrate. A third portion of the resin portion is overlapped with the first and second semiconductor elements.