Semiconductor Unit-Cell Layout With Dual-Surface Wiring
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high integration density and design flexibility due to complex and highly integrated structures, which affect reliability and performance.
Innovation Solution
A semiconductor device design featuring a substrate with specific active patterns, gate structures, and wiring patterns on both surfaces, along with through-contacts and back wiring patterns, allowing for improved connectivity and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the structure within the semiconductor device is made increasingly complex and highly integrated to meet demands for high reliability, high speed, and multifunctionality, then the performance and reliability are improved, but the design freedom and integration density are reduced
Solution Approach 1:
The patent applies backside power delivery network (BSPDN) technology to route power and signal lines through the backside of the substrate rather than only the front side. This dimensional change allows for increased integration density and design freedom while maintaining high reliability, as the backside wiring can be optimized independently from the front-side active devices.
Solution Approach 2:
The patent segments the wiring functions by separating front-side wiring patterns from backside wiring patterns. The front side handles active device connections while the back side handles power delivery and signaling, allowing each layer to be optimized for its specific function and reducing overall design complexity.
2Reliability
If the structure within the semiconductor device is made increasingly complex and highly integrated to meet demands for high reliability, high speed, and multifunctionality, then the performance is improved, but the integration density is reduced
Solution Approach 1:
By utilizing the backside of the substrate for power and signal routing, the patent effectively adds a third dimension to the wiring architecture. This allows more wiring tracks to be accommodated without increasing the front-side footprint, thereby improving integration density while maintaining performance.
Solution Approach 2:
The backside wiring patterns serve multiple functions simultaneously - providing power delivery, signal transmission, and routing flexibility. This multi-functionality allows the same physical structure to support multiple purposes, increasing integration density without sacrificing performance.
Data Source
AI summary
A semiconductor device includes: first and second unit cell areas adjacent one another in a first direction; a third unit cell area adjacent the first unit cell area in a second direction; a tap cell area arranged with the first unit cell area along the first direction; a bit-line and complementary bit-line each extending in the second direction on a first surface of a substrate and connected to the first and third unit cell areas; and a word-line extending in the first direction on a second surface of the substrate and connected to the first and second unit cell areas. Each of the first to third unit cell areas includes: first and second inverters forming a latch circuit; and first and second pass transistors connecting the latch circuit to the bit-line and complementary bit-line. The tap cell area electrically connects the first and second pass transistors and the word-line.