Semiconductor Heat-Dissipation Structure Using Dual Thermal Vias

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Solution Overview

Problem

Conventional semiconductor devices face challenges in effectively dissipating heat from the active region, leading to performance degradation and reduced lifetime due to excessive heat generation, with narrow heat conduction passages and limited heat sink areas.

Innovation Solution

The semiconductor device incorporates a structure with upper and lower metal layers, vias with thermal conductivity, and a resistor connected through vias to dissipate heat generated in the active region, utilizing existing components for heat dissipation without additional parts, and allowing for easy stacking in a three-dimensional configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If heat is dissipated at die or package level in conventional semiconductor devices, then manufacturing is simpler, but heat dissipation effectiveness is insufficient leading to performance degradation

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidheat dissipation effectiveness
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent transitions from conventional single-level heat dissipation (die or package level) to a multi-dimensional approach by implementing heat dissipation at three distinct levels: active region level (first heat dissipation structure), intermediate level (second heat dissipation structure), and package level (third heat dissipation structure). This hierarchical multi-level architecture enables heat to be dissipated simultaneously at multiple spatial dimensions, resolving the contradiction between manufacturing simplicity and heat dissipation effectiveness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If passages for conducting heat are made narrow or complex in conventional devices, then device integration is improved, but heat dissipation effect is reduced

Engineering Contradiction:
Improvedevice integrationVSAvoidheat dissipation effect
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the heat dissipation function into three independent heat dissipation structures located at different levels (active region, intermediate, and package levels). Each structure operates independently to conduct heat away from the active region, eliminating the need for narrow or complex inter-layer passages while maintaining high device integration. This segmentation allows heat to be conducted through multiple parallel pathways rather than forcing it through constrained channels.

Inventive Principle:
Principle #1Segmentation

3Volume of moving object

If heat sink area is made narrow in conventional devices, then device size is reduced, but heat dissipation to outside is insufficient

Engineering Contradiction:
Improvedevice sizeVSAvoidheat dissipation to outside
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent extends the heat dissipation function into the vertical dimension by implementing heat dissipation structures at three different height levels within the package. The first heat dissipation structure is at the active region level, the second is at an intermediate level, and the third is at the package level. This vertical stacking creates multiple heat sink interfaces with the external environment, dramatically increasing the effective heat dissipation area without expanding the device's footprint area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Reliability

If additional separate components are added for heat dissipation, then heat dissipation performance is improved, but manufacturing cost and volume increase

Engineering Contradiction:
Improveheat dissipation performanceVSAvoidcomponent quantity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the metal layers serving as electrical interconnects also function as heat dissipation structures. The first metal layer connects source/drain regions electrically and simultaneously acts as the first heat dissipation structure. The second metal layer provides both electrical connection and serves as the second heat dissipation structure. The third metal layer at the package level provides both electrical grounding and functions as the third heat dissipation structure. This multi-functionality eliminates the need for separate dedicated heat dissipation components, reducing device complexity and manufacturing cost while maintaining excellent heat dissipation performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances heat dissipation, maintains stable radio frequency performance, prevents performance degradation, and extends device lifetime while reducing manufacturing costs and volume.

Implementation Method 1

a first via (191) which includes a material having thermal conductivity, and a second via (192) which includes a material having thermal conductivity

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20260060071A1Semiconductor device
Publication Date: 2026.02.26 WAVEPIA CO LTD
  • US20260060071A1 patent drawing
  • US20260060071A1 patent drawing
  • US20260060071A1 patent drawing

AI summary

The present disclosure relates to a semiconductor device. A semiconductor device according to one embodiment of the present disclosure includes a lower metal layer, a substrate disposed on the lower metal layer, at least one transistor disposed on the substrate, an insulating layer disposed on the substrate and configured to cover the at least one transistor, an upper metal layer disposed on the insulating layer, a first via which includes a material having thermal conductivity, and a second via which includes a material having thermal conductivity, wherein a source electrode of the at least one transistor is connected to the lower metal layer through the first via and is connected to the upper metal layer through the second via.