Semiconductor Contact Formation via Dummy Gate Self-Aligned Etching
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Solution Overview
Problem
The complexity and difficulty of the semiconductor manufacturing process increase as device integration advances, particularly due to challenges in forming contact holes that are accurately sized and aligned with shrinking source/drain regions, leading to high series resistance and the risk of short circuits.
Innovation Solution
A method is introduced where a dielectric layer is etched on both sides of the dummy gate structure to form a contact hole exposing the source/drain doping region, followed by forming a contact plug and then removing the dummy gate structure to create a gate opening for the gate structure, eliminating the need for additional steps like partial thickness removal and protective layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of the contact hole is reduced to match the shrinking source/drain region size, then the series resistance of the contact plug is reduced, but the critical dimension requirement for photoetching increases and overlay precision must be higher to avoid short circuits
Solution Approach 1:
The dummy gate structure is formed preliminarily before the contact hole formation process. This preliminary structure serves as a reference for subsequent self-aligned etching, enabling the contact hole to be precisely positioned relative to the source/drain region without requiring high overlay precision. The dummy gate acts as a mask that defines the contact hole location automatically, eliminating the need for separate alignment steps.
Solution Approach 2:
The dummy gate structure serves as an intermediary element that facilitates the self-aligned formation of contact holes. By using the dummy gate as a reference structure during the etching process, the method enables precise positioning of contact holes relative to source/drain regions without requiring high overlay precision. The dummy gate mediates between the photoetching process and the final contact hole positioning.
2Manufacturing precision
If additional process steps like partial thickness removal and protective layer formation are added to the gate structure formation process, then the manufacturing precision of contact holes is improved, but the process complexity increases
Solution Approach 1:
The dummy gate structure is selectively removed after serving its purpose as a reference for contact hole formation. This extraction of the dummy gate eliminates the need for subsequent partial thickness removal steps and protective layer formation that would otherwise be required to protect the gate structure during contact hole etching. The dummy gate is taken out once its aligning function is fulfilled.
Solution Approach 2:
The dummy gate structure provides self-alignment functionality during the contact hole formation process. By serving as its own alignment reference, the dummy gate eliminates the need for external alignment marks, separate protective layers, and multiple etching steps. The structure serves multiple functions (placeholder, alignment reference, etch mask) in a self-contained manner, reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This simplifies the process complexity, increases process windows, and avoids the formation of excessively large dummy and gate structures, thereby reducing process difficulty and improving the accuracy of contact hole formation.
Implementation Method 1
etching the dielectric layer on both sides of the dummy gate structure to form a contact hole exposing the source/drain doping region
Implementation Method 2
forming a contact plug in the contact hole, the contact plug being electrically connected to the source/drain doping region
Data Source
AI summary
A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a base, a dummy gate structure being formed on the base, a source/drain doping region being formed in the base on both sides of the dummy gate structure, a dielectric layer being formed on the base exposed by the dummy gate structure, and the dielectric layer covering the source/drain doping region; etching the dielectric layer on both sides of the dummy gate structure to form a contact hole exposing the source/drain doping region; forming a contact plug in the contact hole, the contact plug being electrically connected to the source/drain doping region; after forming the contact plug, removing the dummy gate structure, and forming a gate opening in the dielectric layer; and forming a gate structure in the gate opening. Embodiments of the present disclosure are advantageous to simplify process complexity and increase process windows.