Semiconductor Dummy Pattern Alignment for Moire Suppression
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Solution Overview
Problem
In semiconductor device manufacturing, increased detection sensitivity for defects and particles is hindered by moire interference from dummy patterns, leading to incorrect defect detection and reduced yield, as optimized dummy pattern arrangements in different layers can cause moire patterns to be mistaken for defects.
Innovation Solution
The semiconductor device and manufacturing method involve aligning the central axes of dummy patterns in successive layers perpendicularly to the semiconductor substrate, ensuring that the central axes of second dummy patterns coincide with those of first dummy patterns, thereby suppressing moire interference and allowing for accurate defect detection even with increased sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If detection sensitivity is increased to detect smaller defects and particles, then measurement precision is improved, but moire interference from dummy patterns causes false defect detection and reduces reliability
Solution Approach 1:
The patent applies asymmetry by intentionally misaligning the central axes of dummy patterns between different layers. Instead of perfect alignment that causes moire, the dummy patterns in upper layers are positioned with deliberate offset relative to lower layers, breaking the periodic interference pattern while maintaining the dummy patterns' planarization function.
Solution Approach 2:
The patent resolves the moire problem by introducing dimensional variation in the vertical stacking of dummy patterns. By offsetting dummy patterns in different layers along the vertical dimension rather than aligning them perfectly, the interference pattern is eliminated while maintaining detection sensitivity in the horizontal plane.
2Manufacturing precision
If dummy patterns are arranged to be optimized in respective layers for CMP planarization, then manufacturing precision is improved, but moire patterns are generated that interfere with defect detection
Solution Approach 1:
The patent eliminates moire interference by introducing asymmetric positioning of dummy patterns across layers. The central axes of dummy patterns in different layers are deliberately offset from each other, preventing the formation of periodic interference patterns while maintaining the planarization effectiveness of dummy patterns in each individual layer.
Solution Approach 2:
The patent converts the potentially harmful moire effect into a beneficial solution by deliberately misaligning dummy patterns. This intentional asymmetry prevents moire formation, and the offset arrangement itself becomes the solution to the interference problem while preserving CMP planarization quality.
Data Source
AI summary
To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate.