Semiconductor Dummy Pattern Layout for CMP Dishing and Dicing Blade Clogging
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Solution Overview
Problem
Conventional semiconductor devices experience film thickness variations and dishing issues during the CMP process due to varying polishing speeds, leading to potential chipping and dicing blade clogging when cutting the scribe region.
Innovation Solution
A semiconductor device structure is implemented where the dummy pattern's occupancy ratio in the cutting region is lower than in non-cutting regions, with further reduced occupancy ratios near circuit regions, to minimize mechanical strength and conductive material in the cutting area, thereby reducing dicing blade clogging and stress on non-cutting regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dummy pattern is provided in the scribe region to prevent dishing in CMP process, then film thickness uniformity is improved, but the dicing blade becomes clogged with conductive material causing cutting ability to degrade
Solution Approach 1:
The patent applies local quality by creating different dummy pattern occupancy ratios in different regions of the scribe area. Specifically, the cutting region has a lower dummy pattern occupancy ratio (first occupancy ratio) compared to the non-cutting regions (second occupancy ratio). This localized differentiation allows the cutting region to have reduced conductive material that prevents dicing blade clogging, while non-cutting regions maintain higher occupancy ratios to prevent dishing during CMP processing.
2Manufacturing precision
If the dummy pattern occupancy ratio is increased to prevent dishing, then CMP process quality is improved, but mechanical strength of the substrate decreases leading to more chipping
Solution Approach 1:
The patent implements local quality by strategically placing dummy patterns with varying occupancy ratios in different regions. The cutting region uses a lower first occupancy ratio to maintain substrate mechanical strength and reduce chipping, while non-cutting regions use a higher second occupancy ratio to ensure CMP process quality and prevent dishing. This spatially differentiated approach optimizes both strength and manufacturing precision.
3Manufacturing precision
If uniform dummy pattern is provided throughout the scribe region, then dishing prevention is achieved, but dicing blade life decreases due to continuous clogging
Solution Approach 1:
The patent applies local quality by creating a non-uniform dummy pattern distribution where the cutting region has a lower occupancy ratio than non-cutting regions. This localized reduction in conductive material density in the cutting path minimizes dicing blade clogging and extends blade life, while maintaining sufficient dummy patterns in non-cutting areas to prevent dishing during CMP processing.
4Ease of manufacture
If dummy pattern occupancy ratio is reduced in cutting region, then dicing blade clogging is minimized, but dishing may occur in non-cutting regions
Solution Approach 1:
The patent resolves this contradiction by applying local quality with differentiated dummy pattern occupancy ratios. The cutting region uses a lower first occupancy ratio to minimize dicing blade clogging and maintain ease of manufacture, while non-cutting regions use a higher second occupancy ratio to prevent dishing and ensure manufacturing precision. This regional differentiation allows both requirements to be satisfied simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents dishing in the CMP process, reduces chipping, and extends the life of the dicing blade by minimizing clogging and stress on the semiconductor substrate during the dicing process.
Implementation Method 1
The metal film deposited over the entire surface of the semiconductor substrate is subjected, for example, to a chemical mechanical polishing (CMP) process for removal of unnecessary part thereof
Data Source
AI summary
A semiconductor device includes: a circuit region having a function element formed on a semiconductor substrate; a scribe region located between the circuit region and another circuit region formed spaced from the circuit region, the scribe region including a cutting region and non-cutting regions provided at both sides of the cutting region; a first interlayer insulating film formed in the scribe region on the semiconductor substrate; a first dummy pattern made of conductive material and formed in the first interlayer insulating film in the cutting region; and a second dummy pattern made of conductive material and formed in the first interlayer insulating film in each of the non-cutting regions. The ratio, per unit area, of the area of the first dummy pattern to the area of the cutting region is lower than the ratio, per unit area, of the area of the second dummy pattern to the area of the non-cutting regions.