Semiconductor Edge Encapsulation for Higher Breakdown Voltage
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Solution Overview
Problem
Semiconductor devices are limited in their ability to withstand high standoff voltage bias due to the electric field strength of dielectric materials and the electrical path length between opposing terminals, preventing them from achieving higher breakdown voltages.
Innovation Solution
Encapsulating the sidewalls of semiconductor devices with dielectric materials having high electric field strength, such as thermal oxide, silicon nitride, and high temperature polymers, to confine electric fields and eliminate conductive paths in air, thereby increasing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric materials are used for electrical isolation, then the device structure is simple and easy to manufacture, but the breakdown voltage is limited due to insufficient electric field strength
Solution Approach 1:
The patent applies composite materials by combining multiple dielectric layers with different properties (low-k dielectric material for stress control and high-k dielectric material for enhanced electric field strength) to achieve both high breakdown voltage and stress control, resolving the contradiction between reliability improvement and device complexity
Solution Approach 2:
The patent applies local quality by placing high-k dielectric material specifically at critical regions where high electric field strength is needed (such as near terminals or high-stress areas), while using low-k dielectric material in other regions, thereby achieving localized enhancement of breakdown voltage without unnecessarily increasing overall device complexity
2Reliability
If the electrical path length between opposing terminals is increased to withstand higher voltages, then the breakdown voltage increases, but the device size and complexity increase
Solution Approach 1:
The patent uses composite dielectric materials with different dielectric constants to achieve higher breakdown voltage without proportionally increasing the electrical path length. The high-k dielectric layer provides enhanced electric field strength, allowing shorter path lengths to achieve the same voltage withstand capability
Solution Approach 2:
The patent changes the dielectric constant parameter of the isolation material from conventional low-k values to high-k values in strategic locations, which increases the electric field strength and allows for shorter electrical path lengths while maintaining high breakdown voltage capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The encapsulation technique allows semiconductor devices to withstand voltages of 500 volts or more, enhancing their performance in applications requiring kilovolt or multi-kilovolt bias voltages.
Implementation Method 1
one or more encapsulation materials having high field strength that encapsulate sidewalls of the silicon substrate to enable withstanding standoff voltages between components on the semiconductor device of 500 volts or more
Data Source
AI summary
A semiconductor device architecture includes a silicon substrate having sidewalls that are passivated by encapsulating the sidewalls in dielectric materials having high electric field strength. Encapsulating all the sidewalls using high field strength dielectric materials eliminates electrical paths in air or vacuum and confines the electric fields in these high field strength materials, increasing the breakdown voltage relative to unencapsulated devices and allowing the device to withstand greater standoff voltages. In some cases, encapsulating the sidewalls in this manner can allow the device to withstand voltages of 500V or greater.