Semiconductor Edge-Aligned Metal Connection for Parasitic Inductance Reduction

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Solution Overview

Problem

Semiconductor devices with switching converters face issues of high frequency EMI and voltage overshoot due to parasitic inductance in RLC resonance loops, which are not effectively mitigated by existing technologies.

Innovation Solution

A metal connection is implemented on the RDL of a semiconductor die to connect the high-side and low-side power switches, positioned along and proximate to the edge of the semiconductor device where the input voltage pin is distributed, thereby reducing parasitic inductance in the RLC resonance loop.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a conventional RLC resonance loop is used with standard lead frame connections, then the switching converter can be manufactured with standard processes, but parasitic inductance causes high frequency EMI and voltage overshoot

Engineering Contradiction:

Improvehigh frequency EMI and voltage overshootVSAvoidmetal connection layout on semiconductor die

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The metal connection is positioned along and proximate to an edge of the semiconductor die, utilizing the edge dimension to create a compact resonance loop. This edge-aligned configuration reduces the loop area by leveraging the die perimeter, thereby minimizing parasitic inductance without complicating the overall device structure

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The metal connection is specifically positioned only where needed - along the edge proximate to the input voltage pin distribution - rather than requiring a complete redesign of the entire lead frame structure. This localized optimization reduces parasitic inductance in the critical resonance loop while maintaining standard manufacturing processes elsewhere

Inventive Principle:

Principle #3Local quality

2Length of stationary object

If the resonance loop is shortened by repositioning metal connections, then parasitic inductance is reduced, but the manufacturing process becomes more complex

Engineering Contradiction:

Improveresonance loop lengthVSAvoidsemiconductor die fabrication process

Core Design Contradiction:

Length of stationary objectVSEase of manufacture

Solution Approach 1:

The metal connection is segmented into specific regions on the semiconductor die - particularly along the edge proximate to the input voltage pin - allowing the resonance loop to be shortened in the critical area while leaving other areas of the die unchanged for standard manufacturing processes

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10083930B2Semiconductor device reducing parasitic loop inductance of system

Publication Date: 2018.09.25 MONOLITHIC POWER SYSTEMS INC

AI summary

A semiconductor device reducing parasitic loop inductance of system for the switching converter. The semiconductor device has an input voltage pin, a ground reference pin, a switching pin, and a semiconductor die, wherein the semiconductor die comprises a high-side power switch and a low-side power switch and a metal connection. The metal connection directly connects the high-side power switch and the first terminal of the low-side power switch, and is along and proximity to an edge of the semiconductor device to which the input voltage pin is distributed.