3D Semiconductor Memory With Edge Portions
Solution Overview
Problem
The challenge in achieving low-cost, mass-production of three-dimensional (3D) semiconductor memory devices with reliability comparable to their two-dimensional counterparts, due to manufacturing obstacles and high costs associated with fine pattern forming technologies.
Innovation Solution
A semiconductor device design featuring vertically stacked gate electrodes, insulating patterns, active pillars, and memory patterns, with capping sacrificial patterns and buffer oxide patterns, which include edge portions and protrusions to enhance electrical field concentration and charge retention, allowing for improved reliability and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If three-dimensional semiconductor memory devices are manufactured using fine pattern forming technology, then integration density is improved, but manufacturing cost increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple gate electrodes are stacked vertically over active pillars, enabling higher integration density without requiring further reduction of pattern dimensions. This dimensional change allows continued scaling while avoiding the exponentially increasing costs of finer lithography processes.
Solution Approach 2:
The memory structure is segmented into multiple discrete layers including alternating gate electrodes and insulating patterns stacked vertically. This segmentation into manageable layers simplifies the manufacturing process compared to creating increasingly fine two-dimensional patterns, as each layer can be formed using standard deposition and etching processes.
2Manufacturing precision
If three-dimensional semiconductor memory devices are manufactured using fine pattern forming technology, then integration density is improved, but device complexity increases
Solution Approach 1:
By moving to three-dimensional stacking, the patent achieves higher integration density without requiring more complex two-dimensional patterning. The vertical stacking of alternating conductive and insulating layers creates a modular structure that, while three-dimensional, uses well-established semiconductor fabrication processes.
Solution Approach 2:
Insulating patterns are introduced as intermediary layers between gate electrodes in the vertical stack. These insulating layers serve as both electrical isolators and structural templates during fabrication, simplifying the formation of the three-dimensional structure by providing a self-aligned framework for subsequent processing steps.
3Reliability
If edge portions are provided on gate electrodes to concentrate electric fields, then charge retention is improved, but device complexity increases
Solution Approach 1:
Edge portions are provided only at specific locations on the gate electrodes where electric field concentration is needed for effective charge retention during erase operations. This local modification rather than global structural change achieves the reliability improvement with minimal increase in overall device complexity.
Solution Approach 2:
The edge portions of the gate electrodes are formed with curved or rounded profiles rather than sharp corners. This curvature concentrates the electric field at the edges during erase operations, improving charge retention while the smooth transitions reduce manufacturing complexity compared to more complex three-dimensional shapes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the reliability and integration density of 3D semiconductor memory devices by concentrating electric fields and preventing charge loss during erase operations, thereby improving charge retention and reducing manufacturing costs.
Implementation Method 1
edge portions extending between the memory pattern and the insulating patterns... concentrating electric fields
Data Source
AI summary
Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes, an active pillar provided to penetrate the gate electrodes and the insulating patterns and electrically coupled with the substrate, and a memory pattern provided between the gate electrodes and the active pillar and between the insulating patterns and the active pillar. The gate electrodes include edge portions extending between the memory pattern and the insulating patterns.