Semiconductor EMI Protection via Ferrite Layers
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in scaling down dimensions while maintaining quality, yield, performance, and reliability, particularly in addressing issues related to electromagnetic interference and parasitic capacitance.
Innovation Solution
A semiconductor device design incorporating a connection structure with multiple protection layers formed from materials like manganese-zinc ferrite and a porous alleviation layer to reduce electromagnetic interference and alleviate parasitic capacitance, along with a method for fabricating such a device involving specific layer formations and bonding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used for scaling down semiconductor devices, then manufacturing complexity increases, but electromagnetic interference protection and parasitic capacitance control deteriorate
Solution Approach 1:
The patent combines multiple functions into the connection structure: conductive plates for electrical connection, protection layers for EMI shielding, and alleviation layers for parasitic capacitance reduction. This integration resolves the contradiction by achieving enhanced reliability without proportionally increasing fabrication complexity, as all these features are formed within the same connection structure fabrication process.
Solution Approach 2:
The patent employs composite material structures in the connection layers, combining conductive materials with ferrite-based protection layers and porous alleviation materials. This composite approach provides simultaneous EMI protection and parasitic capacitance control while maintaining a unified fabrication process, thus improving reliability without excessive complexity increase.
2Reliability
If connection structures are added for EMI protection, then electromagnetic interference protection improves, but parasitic capacitance increases
Solution Approach 1:
The patent introduces porous alleviation layers with specific local properties (high porosity, low dielectric constant) positioned between conductive plates. This local quality modification reduces parasitic capacitance in critical areas while maintaining EMI protection functionality, thereby resolving the contradiction between EMI shielding and parasitic capacitance reduction.
Solution Approach 2:
The patent utilizes porous materials for the alleviation layers, which have low dielectric constants due to their porous structure. These porous layers reduce parasitic capacitance between conductive plates while still providing EMI protection, directly addressing the contradiction by using material structure to simultaneously achieve both goals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces electromagnetic interference and improves performance by utilizing protection layers and a porous alleviation layer, enhancing the reliability and yield of semiconductor devices.
Implementation Method 1
an alleviation layer positioned in the connection dielectric layer... The alleviation layer is porous... a porosity of the alleviation layer is between about 25% and about 100%
Data Source
AI summary
The present disclosure provides a method for fabricating a semiconductor device including providing a first semiconductor die, forming a connection dielectric layer above the first semiconductor die, forming a first bottom protection layer in the connection dielectric layer, forming a first conductive plate on the first bottom protection layer, and forming a first top protection layer on the first conductive plate. The first bottom protection layer and the first top protection layer are formed of manganese-zinc ferrite, nickel-zinc ferrite, cobalt ferrite, strontium ferrite, barium ferrite, lithium ferrite, lithium-zinc ferrite, single crystal yttrium iron garnet, or gallium substituted single crystal yttrium iron garnet.