Semiconductor Encoder Using Duo-Binary PAM-4 for Signal Integrity

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Solution Overview

Problem

Existing signal modulation methods, such as non-return to zero (NRZ) encoding, struggle to meet the demands for high-capacity and high-speed data transmission required for applications like artificial intelligence and high-definition video streaming.

Innovation Solution

A semiconductor device employing duo-binary PAM-4 encoding and decoding using half-rate or quarter-rate clock signals to encode and decode data, ensuring sufficient eye opening and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If PAM-4 encoding is used to increase data transmission capacity, then data transmission rate is improved, but signal integrity deteriorates due to increased crosstalk and channel insertion loss

Engineering Contradiction:
Improvedata transmission rateVSAvoidsignal integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the high-rate PAM-4 signal transmission into multiple lower-rate transmissions using duo-binary encoding. By dividing the data stream and transmitting at reduced rates with repeated symbols, the system maintains signal integrity while achieving high effective data rates through coding gain rather than raw symbol rate increase.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the encoding parameters from conventional PAM-4 to duo-binary PAM-4, which uses different symbol mapping and repetition patterns. This parameter change allows the system to achieve spectral efficiency comparable to PAM-4 while reducing the Nyquist frequency and minimizing crosstalk and channel insertion loss effects.

Inventive Principle:
Principle #35Parameter changes

2Speed

If higher clock rates are used to achieve faster data transmission, then data transmission speed is improved, but power consumption increases

Engineering Contradiction:
Improvedata transmission speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent employs periodic repetition of data symbols in the duo-binary encoding scheme. By repeating symbols over multiple clock cycles at lower rates rather than transmitting at continuously high clock rates, the system achieves the same effective data transmission speed with reduced instantaneous power consumption and heat generation.

Inventive Principle:
Principle #19Periodic action

3Productivity

If PAM-4 encoding is used to increase data capacity, then bandwidth utilization is improved, but crosstalk and channel insertion loss increase

Engineering Contradiction:
Improvedata capacityVSAvoidcrosstalk and channel insertion loss
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent segments the data transmission into repeated symbol groups using duo-binary encoding. This segmentation allows the receiver to accumulate signal energy over multiple cycles and perform differential decoding, which compensates for crosstalk and insertion loss that would otherwise accumulate in high-rate PAM-4 transmission.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements differential encoding where each symbol's meaning depends on the previous symbol state. This feedback mechanism allows the receiver to detect transitions rather than absolute levels, making the system more robust against crosstalk and channel insertion loss that would otherwise corrupt the signal.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12401553B2Semiconductor device
Publication Date: 2025.08.26 SAMSUNG ELECTRONICS CO LTD
  • US12401553B2 patent drawing
  • US12401553B2 patent drawing
  • US12401553B2 patent drawing

AI summary

An example embodiment of the present invention provides a semiconductor device including: an encoder configured to receive a plurality of bit data by dividing the plurality of bit data into first group data and second group data, the plurality of bit data being divided into 2-bit units, to delay the second group data for a first period, and to output the first group data and the delayed second group data; and an output driver configured to output the first group data and the delayed second group data together to an external semiconductor device.