Semiconductor ESD Protection Layout With SCR Trigger Before Breakdown
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Solution Overview
Problem
Existing semiconductor devices face challenges in effectively protecting internal semiconductor elements from electrostatic discharge (ESD) due to high trigger voltages in ESD protection circuits, which can lead to damage during ESD events.
Innovation Solution
The semiconductor device incorporates a PNP transistor and an NPN transistor with their bases electrically connected, forming an SCR circuit that is triggered before avalanche breakdown occurs, and includes a diode to reduce parasitic capacitance and improve turn-on performance, allowing for a lower trigger voltage and effective ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an ESD protection circuit is designed with conventional structures, then it can provide basic protection functionality, but the trigger voltage becomes too high and may cause damage during ESD events
Solution Approach 1:
The ESD protection circuit is divided into multiple functional regions: a first region with P-type active regions and N-type well regions forming PNP transistors, and a second region with N-type active regions and P-type well regions forming NPN transistors. This segmentation allows independent optimization of each transistor type to achieve lower trigger voltage while maintaining protection effectiveness.
Solution Approach 2:
The patent combines PNP and NPN transistor circuits into a single ESD protection structure, where the PNP transistors and NPN transistors work together synergistically. The merging of these complementary transistor types enables the circuit to trigger at lower voltages compared to conventional single-type transistor designs.
2Device complexity
If the ESD protection circuit uses conventional designs, then the structure remains simple, but parasitic capacitance increases causing signal distortion
Solution Approach 1:
The patent applies different doping concentrations and structural configurations to specific regions: the P-type active regions have optimized doping levels, the N-type well regions have specific depth and concentration profiles, and similar optimizations are applied to the NPN transistor regions. This local quality optimization reduces parasitic capacitance in critical areas while maintaining overall structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the trigger voltage of the ESD protection circuit to a level below the breakdown voltage, effectively protecting internal semiconductor elements from ESD and minimizing signal distortion by reducing parasitic capacitance.
Implementation Method 1
triggered before avalanche breakdown occurs
Implementation Method 2
a first well region formed in the substrate and doped with second conductivity-type impurities, different from the first conductivity-type impurities, a plurality of first active regions disposed in the first well region, doped with the first conductivity-type impurities
Data Source
Figure 1~2
Figure 3
Figure 4~5
AI summary
A semiconductor device 100 includes a substrate 101 doped with first conductivity-type impurities, a first well 102 doped with second conductivity-type impurities different from the first conductivity-type impurities, first active regions 111 in the first well 102, the first active regions 111 being doped with the first conductivity-type impurities and connected to a first pad P1 through a first interconnection, second active regions 112 outside the first well 102, the second active regions 112 being doped with the second conductivity-type impurities and connected to a second pad P2 through a second interconnection, third active regions 113 alongside the first active regions 111 in the first well 102 and doped with the second conductivity-type impurities, and fourth active 114 regions alongside the second active regions 112 outside the first well 102 and doped with the first conductivity-type impurities, wherein at least one of the third active regions 113 and at least one of the fourth active regions 114 are electrically connected to each other through a third interconnection.