Functional Component Within Interconnect Structure of Semiconductor Device and Method of Forming Same
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, challenges arise in maintaining the integrity of conductive features during planarization processes, leading to issues like dishing or erosion of metallization layers and conductive vias, which affect the integration density and reliability of electronic components.
Innovation Solution
The implementation of a combined etch stop layer and CMP stop layer, made of specific dielectric materials, which aids in forming through substrate vias and conductive interconnects while preventing dishing or erosion by controlling the planarization process and ensuring uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If planarization process is performed to achieve flat surface for subsequent processing, then surface uniformity is improved, but dishing or erosion of conductive features occurs
Solution Approach 1:
An etch stop layer is introduced as an intermediary layer between the dielectric layer and the conductive features. This layer acts as a protective mediator during the planarization process, preventing direct contact between the CMP polishing tools and the conductive features, thereby avoiding dishing and erosion while still enabling surface uniformity to be achieved.
Solution Approach 2:
The etch stop layer is deposited beforehand to provide a cushioning protective layer over the conductive features before the planarization process begins. This pre-positioned layer absorbs the mechanical stress and polishing action, preventing damage to the underlying conductive structures while allowing the dielectric surface to be planarized.
2Productivity
If minimum feature size is reduced to increase integration density, then integration density is improved, but process control difficulty increases
Solution Approach 1:
The invention introduces a specific layer thickness parameter for the etch stop layer that is optimized for miniaturized features. By controlling the thickness of this protective layer to be greater than the thickness of the conductive features, the process becomes more controllable even as feature sizes decrease, enabling continued scaling while maintaining process reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively integrates process steps for forming interconnect structures, preventing dishing or erosion of conductive features and enhancing the integration density and reliability of semiconductor devices by maintaining the integrity of metallization layers and conductive vias.
Implementation Method 1
performing a planarization process on the conductive material to expose the second dielectric layer
Data Source
AI summary
A semiconductor device includes a substrate. A first dielectric layer is over the substrate. A first interconnect is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and the first interconnect. A conductive via extends through the first dielectric layer, the second dielectric layer and the substrate. A topmost surface of the conductive via is level with a topmost surface of the second dielectric layer. A third dielectric layer is over the second dielectric layer and the conductive via. A fourth dielectric layer is over the third dielectric layer. A second interconnect is in the fourth dielectric layer. The second interconnect extends through the third dielectric layer and the second dielectric layer and physically contacts the first interconnect.