Semiconductor Etching with Separate By-Product Heating for CFET Trenches
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating stacked device configurations, such as CFETs, due to the introduction of additional features as minimum feature sizes are reduced, leading to issues in etching processes that affect the precision and consistency of semiconductor nanostructures.
Innovation Solution
The use of dummy nanostructures with high etching selectivity, combined with a controlled etching process involving a secondary heating element to manage by-products, ensures precise etching of semiconductor nanostructures in CFETs, maintaining structural integrity and reducing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but additional features are introduced that complicate the fabrication process and affect etching precision
Solution Approach 1:
The patent applies segmentation by dividing the etching process into multiple distinct etching operations, each targeting specific material layers with customized etching conditions. This allows precise control over the removal of different materials (e.g., dummy nanostructures versus semiconductor nanostructures) while maintaining high integration density, thereby resolving the contradiction between productivity and manufacturing precision
Solution Approach 2:
The patent utilizes parameter changes by adjusting etching process parameters (such as gas composition, power, pressure, and temperature) between different etching steps to achieve selective removal of materials. This enables precise control over etching rates and selectivity, allowing the process to handle additional features introduced by reduced minimum feature sizes while maintaining etching precision
2Manufacturing precision
If dummy nanostructures are added to improve etching selectivity, then etching precision is enhanced, but device structure complexity increases
Solution Approach 1:
The patent applies the taking out principle by selectively removing dummy nanostructures through targeted etching processes after they have served their purpose of providing etching selectivity. The dummy nanostructures are extracted from the final device structure, allowing the process to benefit from their presence during fabrication while avoiding the penalty of their permanent inclusion in the device, thus reducing overall structure complexity
Solution Approach 2:
The dummy nanostructures serve as intermediaries during the fabrication process, facilitating selective etching of underlying layers. They are temporarily introduced to enable precise etching control, then removed after completing their mediating function. This approach allows etching precision to be enhanced without permanently increasing device structure complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise and consistent etching of semiconductor nanostructures, enhancing the fabrication of CFETs by minimizing interference from by-products and ensuring uniformity in feature sizes.
Implementation Method 1
heating the by-product with a laser
Implementation Method 2
reacting the dielectric material to form a gas and recess the dielectric material, the reacting the dielectric material additionally creating a by-product
Data Source
AI summary
A method of manufacturing semiconductor devices, the semiconductor devices manufactured, and apparatuses for forming the semiconductor devices are described in which by-products from etching processes are independently heated separately from a semiconductor wafer. In embodiments a dielectric material is deposited into a trench over a semiconductor substrate and the dielectric material is recessed with an etching process. The etching process includes heating the semiconductor substrate and separately heating a by-product of the etching process.